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LMX2364 Datasheet(Fiches technique) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numéro de pièce LMX2364
Description  2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer
Télécharger  39 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
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LMX2364 Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Pin Descriptions
Pin Number
Pin
Description
TSSOP
SLE
2
1
VccRF
RF PLL power supply voltage input. Must be equal to V
VccIF. May range from 2.7V to
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
3
2
VcpRF
Power supply for RF charge pump. Must be
≥ V
VccRF and VVccIF.
4
3
CPoutRF
RF charge pump output.
5
4
GND
Ground for RF PLL digital circuitry.
6
5
FinRF
RF prescaler input. Small signal input from the VCO.
7
6
FinRF*
RF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
8
7
GND
Ground for RF PLL analog circuitry.
9
8
OSCinRF
RF R counter input. Has a V
CC/2 input threshold when configured as an input and can
be driven from an external CMOS or TTL logic gate.
10
9
OSCinIF
Oscillator input which can be configured to drive both the IF and RF R counter inputs
or only the IF R counter depending on the state of the OSC programming bit.
11
10
Ftest/LD
Programmable multiplexed output pin. Can function as general purpose CMOS
TRI-STATE® I/O, analog lock detect output, digital filtered lock detect output, orN&R
divider output.
12
11
ENRF
RF PLL Enable. Powers down RF N and R counters, prescaler, and TRI-STATE
charge pump output when LOW, regardless of the state RF_PD bit. Bringing ENRF
high powers up RF PLL depending on the state of RF_PD control bit.
13
12
ENIF
IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the
charge pump output when LOW, regardless of the state IF_PD bit. Bringing ENIF high
powers up IF PLL depending on the state of IF_PD control bit.
14
13
CLK
High impedance CMOS Clock input. Data for the control registers is clocked into the
24-bit shift register on the rising edge.
15
14
DATA
Binary serial data input. Data entered MSB first. The last three bits are the control
bits. High impedance CMOS input.
16
15
LE
Latch enable. High impedance CMOS input. Data stored in the shift register is loaded
into one of the 7 internal latches when LE goes HIGH.
17
16
GND
Ground for IF analog circuitry.
18
17
FinIF*
IF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground.
19
18
FinIF
IF prescaler input. Small signal input from the VCO.
20
19
GND
Ground for IF digital circuitry.
21
20
CPoutIF
IF charge pump output.
22
21
VcpIF
Power supply for IF charge pump. Must be
≥ V
VccRF and VVccIF.
23
22
VccIF
IF power supply voltage input. Must be equal to V
VccRF. Input may range from 2.7V to
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
24
23
FLoutIF
IF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
1
24
FLoutRF
RF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
www.national.com
3


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