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CDCE813QPWRQ1 Fiches technique(PDF) 6 Page - Texas Instruments |
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CDCE813QPWRQ1 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 29 page 6 CDCE813-Q1 SNAS705 – JANUARY 2017 www.ti.com Product Folder Links: CDCE813-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN TYP(1) MAX UNIT (2) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2). (3) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider. (4) odc depends on the output rise and fall time (tr and tf); data sampled on the rising edge (tr) LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V, II = –18 mA –1.2 V II LVCMOS input current VI = 0 V or VDD, VDD = 1.9 V ±5 μA IIH LVCMOS input current for S0, S1, and S2 VI = VDD, VDD = 1.9 V 5 μA IIL LVCMOS input current for S0, S1, and S2 VI = 0 V, VDD = 1.9 V –4 μA CI Input capacitance at Xin/CLK VIClk = 0 V or VDD 6 pF Input capacitance at Xout VIXout = 0 V or VDD 2 Input capacitance at S0, S1, and S2 VIS = 0 V or VDD 3 CDCE813-Q1, LVCMOS PARAMETER FOR VDDOUT = 3.3-V MODE VOH LVCMOS high-level output voltage VDDOUT = 3 V, IOH = –0.1 mA 2.9 V VDDOUT = 3 V, IOH = –8 mA 2.4 VDDOUT = 3 V, IOH = –12 mA 2.2 VOL LVCMOS low-level output voltage VDDOUT = 3 V, IOL = 0.1 mA 0.1 V VDDOUT = 3 V, IOL = 8 mA 0.5 VDDOUT = 3 V, IOL = 12 mA 0.8 tPLH, tPHL Propagation delay PLL bypass 3.2 ns PLL enabled (fCLK = fVCO), 70 MHz ≤ fVCO ≤ 85 MHz 1.6 4.3 tr, tf Rise and fall time VDDOUT = 3.3 V (20%–80%) 0.6 ns tjit(cc) Cycle-to-cycle jitter(2) 1 PLL switching, Y2-to-Y3, 10,000 cycles 50 200 ps tjit(per) Peak-to-peak period jitter(2) 1 PLL switching, Y2-to-Y3 60 200 ps tsk(o) Output skew (see Table 2)(3) fOUT = 50 MHz, Y1-to-Y3 440 ps odc Output duty cycle (4) fVCO = 100 MHz, Pdiv = 1 45% 55% CDCE813-Q1, LVCMOS PARAMETER FOR VDDOUT = 2.5-V MODE VOH LVCMOS high-level output voltage VDDOUT = 2.3 V, IOH = –0.1 mA 2.2 V VDDOUT = 2.3 V, IOH = –6 mA 1.7 VDDOUT = 2.3 V, IOH = –10 mA 1.6 VOL LVCMOS low-level output voltage VDDOUT = 2.3 V, IOL = 0.1 mA 0.1 V VDDOUT = 2.3 V, IOL = 6 mA 0.5 VDDOUT = 2.3 V, IOL = 10 mA 0.7 tPLH, tPHL Propagation delay PLL bypass 3.6 ns tr, tf Rise and fall time VDDOUT = 2.5 V (20%–80%) 0.8 ns tjit(cc) Cycle-to-cycle jitter(2) 1 PLL switching, Y2-to-Y3, 10,000 cycles 50 200 ps tjit(per) Peak-to-peak period jitter(2) 1 PLL switching, Y2-to-Y3 60 200 ps tsk(o) Output skew (see Table 2)(3) fOUT = 50 MHz, Y1-to-Y3 440 ps odc Output duty cycle(4) fVCO = 100 MHz, Pdiv = 1 45% 55% |
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