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ADV7613 Fiches technique(PDF) 9 Page - Analog Devices |
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ADV7613 Fiches technique(HTML) 9 Page - Analog Devices |
9 / 14 page ADV7613 Data Sheet Rev. A | Page 8 of 13 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No Mnemonic Type Description A1, A4, A10, B4, C4, C5, D4, D5, E4, E5, F4 to F6, G4 to G6, H4, H5, K1, K10 GND Ground Ground. A2 DDCA_SDA HDMI Rx DDC HDCP Slave Serial Data for HDMI Port A. A3 DDCA_SCL HDMI Rx DDC HDCP Slave Serial Clock for HDMI Port A. A5 XTALP Miscellaneous analog Input for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7613. A6 PVDD Power Digital PLL Supply Voltage (1.8 V). A7 RESET Miscellaneous digital System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7613 circuitry. A8 SCL Miscellaneous digital I2C Port Serial Clock Input. SCL is the clock line for the control port. A9 AP5 Audio output Audio Output Pin 5. This pin is configurable to output S/PDIF digital audio, HBR or DSD. The AP5 pin typically provides the LRCLK signal for the I2S modes. B1 RXA_5V HDMI input 5 V Detect Pin for HDMI Port A. A GND DDCA_SD A DDCA_SCL GND XTALP PVDD RESET SCL AP5 GND A B RXA_5V HPA_A CEC GND XTALN CS INT SDA AP4 AP3 B C RXA_C+ RXA_C– CVDD GND GND DVDD TEST0 TEST1 AP2 AP1 C D RXA_0+ RXA_0– CVDD GND GND DVDD TEST2 TEST3 MCLKOUT SCLK D E RXA_1+ RXA_1– CVDD GND GND DVDD DVDD TEST4 TEST5 AP0 E F RXA_2+ RXA_2– TVDD GND GND GND DVDDIO TEST6 TEST7 TEST8 F G CVDD CVDD TVDD GND GND GND DVDDIO TEST9 TEST10 TEST11 G H LTX_VDD LTX_VDD GND GND LTX_VDD LTX_VDD TEST12 TEST13 H J J K GND GND TEST PINS POWER SUPPLIES DATA LINES (INPUT AND OUTPUT) GND K 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 LTX2_0+ LTX2_0– LTX2_1+ LTX2_1– LTX2_2+ LTX2_2– LTX2_3+ LTX2_3– LTX2_C+ LTX2_C– LTX1_0+ LTX1_0– LTX1_1+ LTX1_1– LTX1_2+ LTX1_2– LTX1_3+ LTX1_3– LTX1_C+ LTX1_C– |
Numéro de pièce similaire - ADV7613 |
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Description similaire - ADV7613 |
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