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ADV7613 Fiches technique(PDF) 7 Page - Analog Devices |
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ADV7613 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 14 page ADV7613 Data Sheet Rev. A | Page 6 of 13 Parameter Symbol Min Typ Max Unit Start Condition Setup Time t 4 600 ns SDA Setup Time t 5 100 ns SCL and SDA Rise Time t 6 300 ns SCL and SDA Fall Time t 7 300 ns Stop Condition Setup Time t 8 0.6 µs RESET FEATURE Reset Pulse Width 5 ms Reset Pulse to First I2C Transaction 5 ms I2S PORT, MASTER MODE SCLK Mark to Space Ratio t 15:t16 45:55 55:45 % Duty Cycle Left/Right Clock (LRCLK) Data Transition Time t 17 10 ns t 18 10 ns I2Sx1 Data Transition Time t 19 5 ns t 20 5 ns 1 I2Sx signals (where x = 0, 1, 2, or 3) are available on the AP1 to AP4 pins (see Table 6). Timing Diagrams Figure 3. I2C Timing Figure 4. I2S Timing SDA SCL t5 t3 t4 t8 t6 t7 t2 t1 t3 SCLK LRCLK I2Sx LEFT JUSTIFIED MODE I2Sx RIGHT JUSTIFIED MODE I2Sx I2S MODE MSB MSB – 1 t15 t16 t17 t19 t20 t18 MSB MSB – 1 LSB MSB t19 t20 t19 t20 NOTES 1. THE LRCLK SIGNAL IS AVAILABLE ON THE AP5 PIN. 2. I2Sx SIGNALS (WHERE x = 0, 1, 2, OR 3) ARE AVAILABLE ON THE FOLLOWING PINS:AP1, AP2, AP3, AND AP4. |
Numéro de pièce similaire - ADV7613 |
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Description similaire - ADV7613 |
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