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TPS3825-33DBVRG4 Fiches technique(PDF) 10 Page - Texas Instruments

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No de pièce TPS3825-33DBVRG4
Description  Voltage Monitor With Watchdog Timer
Download  29 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS3825-33DBVRG4 Fiches technique(HTML) 10 Page - Texas Instruments

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+
RESET
(1)
RESET
MR
(2)
WDI
(3)
Auto-Reset
Oscillator
Transition
Detector
Watchdog
Timer Logic
RESET
Logic
V
REF
V
DD
52 kW
40 kW
TPS3820, TPS3823, TPS3823A, TPS3824, TPS3825, TPS3828
SLVS165K – APRIL 1998 – REVISED NOVEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The TPS382x family of supervisors provide circuit initialization and timing supervision. Optional configurations
include devices with active-high and active-low output signals (TPS3824/5), devices with a watchdog timer
(TPS3820/3/4/8), and devices with manual reset (MR) pins (TPS3820/3/5/8). RESET asserts when the supply
voltage, VDD, rises above 1.1 V. For devices with active-low output logic, the device monitors VDD and keeps
RESET low as long as VDD remains below the negative threshold voltage, VIT−. For devices with active-high
output logic, RESET remains high as long as VDD remains below VIT−. An internal timer delays the return of the
output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD rises above
the positive threshold voltage (VIT− + VHYS). When the supply voltage drops below VIT−, the output becomes
active (low) again. All the devices of this family have a fixed-sense threshold voltage, VIT–, set by an internal
voltage divider, so no external components are required.
The TPS382x family is designed to monitor supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The devices are
available in a 5-pin SOT-23 package and are characterized for operation over a temperature range of
−40°C to
85°C.
8.2 Functional Block Diagram
(1)
TPS3824/5
(2)
TPS3820/3/5/8
(3)
TPS3820/3/4/8
8.3 Feature Description
8.3.1 Manual Reset (MR)
The MR input allows an external logic signal from processors, logic circuits, and/or discrete sensors to force a
reset signal regardless of VDD with respect to VIT– or the state of the watchdog timer. A low level at MR causes
the reset signals to become active.
8.3.2 Active High or Active Low Output
All TPS382x devices have an active-low logic output (RESET), while the TPS3824/5 devices also include an
active-high logic output (RESET).
8.3.3 Push-Pull or Open-Drain Output
All TPS382x devices, except for TPS3828, have push-pull outputs. TPS3828 devices have an open-drain output.
10
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Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: TPS3820 TPS3823 TPS3824 TPS3825 TPS3828


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