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TPS3851H50EDRBT Fiches technique(PDF) 3 Page - Texas Instruments

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No de pièce TPS3851H50EDRBT
Description  Precision Voltage Supervisor with Integrated Watchdog Timer
Download  31 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS3851H50EDRBT Fiches technique(HTML) 3 Page - Texas Instruments

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1
VDD
8
RESET
2
CWD
7
WDO
3
MR
6
WDI
4
GND
5
SET1
Not to scale
Thermal
Pad
3
TPS3851
www.ti.com
SBVS300 – NOVEMBER 2016
Product Folder Links: TPS3851
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
DRB Package: TPS3851
3-mm × 3-mm VSON-8
Top View
Pin Functions
NAME
NO.
I/O
DESCRIPTION
CWD
2
I
Programmable watchdog timeout input. The watchdog timeout is set by connecting a capacitor between this pin and
ground. Connecting via a 10-kΩ resistor to VDD or leaving unconnected further enables the selection of the preset
watchdog timeouts; see the CWD Functionality section.
The TPS3851 determines the watchdog timeout using either Equation 1 or Equation 2 with standard or extended
timing, respectively.
GND
4
Ground pin
MR
3
I
Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains
low for a fixed reset delay (tRST) time after MR is deasserted (high).
RESET
8
O
Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). RESET goes
low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the
RESET timeout-counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined
below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the
monitored voltage is within the correct operating range (above VITN+VHYST) and the RESET timeout is complete.
SET1
5
I
Logic input. Grounding the SET1 pin disables the watchdog timer. SET1 and CWD select the watchdog timeouts; see
the SET1 section.
VDD
1
I
Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
WDI
6
I
Watchdog input. A falling edge must occur at WDI before the timeout (tWD) expires.
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. WDI is ignored when RESET or
WDO are low (asserted) and when the watchdog is disabled. If the watchdog is disabled, WDI cannot be left
unconnected and must be driven to either VDD or GND.
WDO
7
O
Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). WDO goes
low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout
occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-
impedance state.
Thermal pad
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.


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