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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TP5510N Fiches technique(PDF) 6 Page - National Semiconductor (TI) |
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TP5510N Fiches technique(HTML) 6 Page - National Semiconductor (TI) |
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6 / 12 page  Timing Specifications Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 50V g 5% VBB eb50V g5% TA e 0 Cto70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests andor product design and characterization All signals referenced to GNDA Typicals specified at VCC e 50V VBB eb50V TA e 25 C All timing parameters are measured at VOH e 20V and VOL e 07V See Definitions and Timing Conventions section for test methods information Symbol Parameter Conditions Min Typ Max Units 1tPM Frequency of Master Clocks Depends on the Device Used and the 1536 MHz BCLKD CLKSEL Pin 1544 MHz MCLKE and MCLKD 2048 MHz tDM Rise Time of Master Clock MCLKE and MCLKD 50 ns tFM Fall Time of Master Clock MCLKE and MCLKD 50 ns tPB Period of Bit Clock 485 488 15725 ns tDB Rise Time of Bit Clock BCLKE and BCLKD 50 ns tFB Fall Time of Bit Clock BCLKE and BCLKD 50 ns tWMH Width of Master Clock High MCLKE and MCLKD 160 ns tWML Width of Master Clock Low MCLKE and MCLKD 160 ns tSBFM Set-Up Time from BCLKE High First Bit Clock after the Leading 100 ns to MCLKE Falling Edge Edge of FSE tSFFM Set-Up Time from FSE High Long Frame Only 100 ns to MCLKE Falling Edge tWBH Width of Bit Clock High VIHe22V 160 ns tWBL Width of Bit Clock Low VILe06V 160 ns tHBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync tHBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync tSFB Set-Up Time from Frame Sync Long Frame Only 115 ns to Bit Clock Low tDBD Delay Time from BCLKE High Loade150 pF plus 2 LSTTL Loads 0 140 ns to Data Valid tDBTS Delay Time to TSE Low Loade150 pF plus 2 LSTTL Loads 140 ns tDZC Delay Time from BCLKE Low to CLe0 pF to 150 pF 50 165 ns Data Output Disabled tDZF Delay Time to Valid Data from CLe0 pF to 150 pF 20 165 ns FSE or BCLKE Whichever Comes Later tSDB Set-Up Time from DD Valid to 50 ns BCLKDE Low tHBD Hold Time from BCLKDE Low to 50 ns DD Invalid tSF Set-Up Time from FSED to Short Frame Sync Pulse (1 Bit Clock 50 ns BCLKED Low Period Long) tHF Hold Time from BCLKED Low Short Frame Sync Pulse (1 Bit Clock 100 ns to FSED Low Period Long) tHBFl Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FSE or FSD) tWFL Minimum Width of the Frame 64k Bits Operating Mode 160 ns Sync Pulse (Low Level) http www nationalcom 6 |
Numéro de pièce similaire - TP5510N |
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Description similaire - TP5510N |
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