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FM25160 Fiches technique(PDF) 7 Page - List of Unclassifed Manufacturers

No de pièce FM25160
Description  16Kb FRAM Serial Memory
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Ramtron
FM25160
12 May 2000
7/14
Table 3. Block Memory Write Protection
BP1
BP0
Protected Address Range
0
0
None
0
1
600h to 7FFh (upper ¼)
1
0
400h to 7FFH (upper ½)
1
1
000h to 7FFh (all)
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the affect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the status register. Thus the Status
register is write protected if WPEN=1 and /WP=0.
This scheme provides a write protection mechanism,
which can prevent software from writing the
memory under any circumstances. This occurs if the
BP1 and BP0 are set to 1, then the WPEN bit is set
to 1 and /WP is set to 0. This occurs because the
block protect bits prevent writing memory and the
/WP signal in hardware prevents altering the block
protect bits (if WPEN is high). Therefore in this
condition, hardware must be involved in allowing a
write operation. The following table summarizes the
write protection conditions.
Table 4. Write Protection
WEL
WPEN
/WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
0
Protected
Unprotected
Unprotected
1
0
1
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
Memory Operation
The SPI interface, with its relatively high maximum
clock frequency, highlights the fast write capability of
the FRAM technology. Unlike SPI bus EEPROMs
the FM25160 can perform sequential writes at bus
speed. No page register is needed and any number of
sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The bus master then issues a WRITE op-
code. Part of this op-code includes the upper 3-bits of
the memory address. Bits 5, 4, and 3 in the op-code
correspond to A10, A9, A8 respectively. The next
byte is the lower 8-bits of the address. In total, the 11-
bits specify the address of the first byte of the write
operation. Subsequent bytes are data and they are
written sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks. If the last address of 7FFh is reached, the
counter will roll over to 000h. Data is written MSB
first.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8
th
clock). The rising edge of /CS terminates a
WRITE op-code operation.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Part of this op-code includes the
upper 3-bits of the memory address. The next byte is
the lower 8-bits of the address. In total, the 11-bits
specify the address of the first byte of the read
operation. After the op-code is complete, the SI line
is ignored. The bus master then issues 8 clocks, with
one bit read out for each. Addresses are incremented
internally as long as the bus master continues to issue
clocks. If the last address of 7FFh is reached, the
counter will roll over to 000h. Data is read MSB first.
The rising edge of /CS terminates a READ op-code
operation.. The bus configuration for read and write
operations is shown below.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master takes
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.


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