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CS8402A-CS Fiches technique(PDF) 9 Page - List of Unclassifed Manufacturers

No de pièce CS8402A-CS
Description  Digital Audio Interface Transmitter
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CS8402A-CS Fiches technique(HTML) 9 Page - List of Unclassifed Manufacturers

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digital audio specifications, V = 0 signifies the
audio signal is suitable for conversion to analog.
B1 and B0 select one of three modes for the
buffer memory. The different modes are shown
in Figure 5 and the bit combinations in Table 2.
More information on the different modes can be
found in the Buffer Memory section. Bit 2, CRCE, is
the channel status CRCC enable and should only be
used in professional mode. When CRCE is high, the
0
1
2
3
4
5
6
7
X:02
RST
MUTE
CRCE
M0
M1
V
B1
B0
B1: with B0, selects the buffer memory mode.
V: Validity bit of current sample.
B0: with B1, selects the buffer memory mode.
M1: with M0, selects MCK frequency.
M0: with M1, selects MCK frequency.
CRCE: Channel status CRC Enable. Professional mode only.
MUTE: When clear, transmitted audio data is set to zero.
RST: When clear, drivers are disabled, frame counters cleared.
Figure 8. Control Register 2
0
1
2
3
4
5
6
7
X:01
MASK0
MASK1
MASK2
TRNPT
BKST
MASK1: Interrupt mask for FLAG1.
MASK2: Interrupt mask for FLAG2. A "1" enables the interrupt.
MASK0: Interrupt mask for FLAG0.
BKST: Causes realignment of data block when set to "1".
TRNPT: Selects Transparent Mode appropriately setting data
delay through device
Figure 7. Control Register 1
0
1
2
3
4
5
6
7
X:00
FLAG0
FLAG1
FLAG2
FLAG1: Memory mode dependent - See figure 11
FLAG2: High for first four bytes of channel status
FLAG0: High for last two bytes of user data.
Figure 6. Status Register
01
2
3
User Data
1st Four
Bytes of
C. S. Data
1st Four
Bytes of
C. S. Data
1st Four
Bytes of
Left C. S.
Data
Auxiliary
Data
Last
20 Bytes
Channel
Status
Data
Status register 0
Control Register 1
Control Register 2
Control Register 3
C. S.
Data
Left
C. S.
Data
Right
C. S.
Data
1st Four
Bytes of
Right
C. S. Data
U
N
D
E
F
I
N
E
D
A
D
D
R
E
S
S
Memory Mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Figure 5. CS8401A Buffer Memory Modes
Table 1. MCLK Frequencies
M1
M0
MCLK
00
128
× Input Word Rate
01
192
× Input Word Rate
10
256
× Input Word Rate
11
384
× Input Word Rate
B1
B0
Mode
Buffer Memory Contents
0
0
0
Channel Status
0
1
1
Auxiliary Data
1
0
2
Independent Channel Status
1
1
3
Reserved
Table 2. Buffer Memory Modes
CS8401A
DS60F1
9


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