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9ZXL1950BKLF Datasheet(Fiches technique) 11 Page - Integrated Device Technology

Numéro de pièce 9ZXL1950BKLF
Description  19-output DB1900Z Low-Power Derivative w/85ohm Terminations
Télécharger  18 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

9ZXL1950BKLF Datasheet(HTML) 11 Page - Integrated Device Technology

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REVISION E 11/20/15
11
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
9ZXL1950 SMBus Addressing
SADR(1:0)_tri
SMBus Address (Rd/Wrt bit = 0)
00
D8
0M
DA
01
DE
M0
C2
MM
C4
M1
C6
10
CA
1M
CC
11
CE
SMBusTable: PLL Mode, and Frequency Select Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL Mode 1
PLL Operating Mode Rd back 1
R
Latch
Bit 6
PLL Mode 0
PLL Operating Mode Rd back 0
R
Latch
Bit 5
DIF_18_En
Output Control
RW
Low/Low
Enable
1
Bit 4
DIF_17_En
Output Control
RW
Low/Low
Enable
1
Bit 3
DIF_16_En
Output Control
RW
Low/Low
Enable
1
Bit 2
0
Bit 1
0
Bit 0
100M_133M#
Frequency Select Readback
R
133MHz
100MHz
Latch
SMBusTable: Output Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DIF_7_En
Output Control
RW
1
Bit 6
DIF_6_En
Output Control
RW
1
Bit 5
DIF_5_En
Output Control
RW
1
Bit 4
DIF_4_En
Output Control
RW
1
Bit 3
DIF_3_En
Output Control
RW
1
Bit 2
DIF_2_En
Output Control
RW
1
Bit 1
DIF_1_En
Output Control
RW
1
Bit 0
DIF_0_En
Output Control
RW
1
SMBusTable: Output Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DIF_15_En
Output Control
RW
1
Bit 6
DIF_14_En
Output Control
RW
1
Bit 5
DIF_13_En
Output Control
RW
1
Bit 4
DIF_12_En
Output Control
RW
1
Bit 3
DIF_11_En
Output Control
RW
1
Bit 2
DIF_10_En
Output Control
RW
1
Bit 1
DIF_9_En
Output Control
RW
1
Bit 0
DIF_8_En
Output Control
RW
1
SMBusTable: PLL SW Override Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
PLL_SW_EN
Enable S/W control of PLL BW
RW
HW Latch
SMBus Control
0
Bit 2
PLL Mode 1
PLL Operating Mode 1
RW
1
Bit 1
PLL Mode 0
PLL Operating Mode 1
RW
1
Bit 0
0
Reserved
Reserved
Reserved
Reserved
Reserved
See PLL Operating Mode
Readback Table
Reserved
Low/Low
Enable
Low/Low
Enable
44/43
62/61
60/59
38/37
50/49
42/41
48/47
Byte 2
54/53
17/18
56/55
Byte 3
Note: Setting bit 3 to '1' allows the user to overide the Latch value from pin 4 via use of bits 2 and 1. Use the values from the PLL Operating
Mode Readback Table. Note that Byte 0, Bits 7:6 will keep the value originally latched on pin 4. A warm reset of the system will have to
accomplished if the user changes these bits.
Byte 0
4
4
72/71
68/67
66/65
23/24
19/20
35/36
31/32
29/30
25/26
3
Byte 1
See PLL Operating Mode
Readback Table
Reserved


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