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9ZXL1950BKLF Datasheet(Fiches technique) 9 Page - Integrated Device Technology

Numéro de pièce 9ZXL1950BKLF
Description  19-output DB1900Z Low-Power Derivative w/85ohm Terminations
Télécharger  18 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

9ZXL1950BKLF Datasheet(HTML) 9 Page - Integrated Device Technology

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REVISION E 11/20/15
9
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
Electrical Characteristics–Phase Jitter Parameters
Test Loads
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
34
86
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.2
3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.1
3.1
ps
(rms)
1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
1
ps
(rms)
1,2,4
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.2
0.5
ps
(rms)
1,5
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.1
0.3
ps
(rms)
1,5
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.1
0.2
ps
(rms)
1,5
tjphPCIeG1
PCIe Gen 1
0.1
10
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1
0.3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.1
0.7
ps
(rms)
1,2,6
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.0
0.3
ps
(rms)
1,2,4,6
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.0
0.3
ps
(rms)
1,5,6
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.0
0.1
ps
(rms)
1,5,6
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.0
0.1
ps
(rms)
1,5,6
1 Applies to all outputs.
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.4
Additive Phase Jitter,
Bypass mode
tjphPCIeG2
tjphQPI_SMI
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Subject to final ratification by PCI SIG.
Phase Jitter, PLL Mode
tjphPCIeG2
tjphQPI_SMI
Zo = 85
 Dif.,
10 inches
LP-HCSL
Differential
Output
9ZXL Differential Test Loads
Rs
Rs
2pF
2pF
Differential Output Terminations
DIF Zo (Ω)Rs (Ω)
85
Internal
100
7.5
(External)


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