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9ZXL1950BKLF Fiches technique(PDF) 3 Page - Integrated Device Technology

No de pièce 9ZXL1950BKLF
Description  19-output DB1900Z Low-Power Derivative w/85ohm Terminations
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

9ZXL1950BKLF Fiches technique(HTML) 3 Page - Integrated Device Technology

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REVISION E 11/20/15
3
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
VDDA
PWR
Power for the PLL core.
2
GNDA
GND
Ground pin for the PLL core.
3
^100M_133M#
IN
3.3V Input to select operating frequency. This pin has an internal pull-up resistor.
See Functionality Table for Definition
4
^vHIBW_BYPM_LOBW#
LATCHE
D IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
5
CKPWRGD_PD#
IN
3.3V Input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
6
GND
GND
Ground pin.
7VDDR
PWR
3.3V power for differential input clock (receiver). This VDD should be treated as
an analog power rail and filtered appropriately.
8
DIF_IN
IN
HCSL True input
9
DIF_IN#
IN
HCSL Complementary Input
10
^SADR0_tri
IN
SMBus address bit. This is a tri-level input that works in conjunction with the
SADR1 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up
resistor.
11
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
12
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
13
^SADR1_tri
IN
SMBus address bit. This is a tri-level input that works in conjunction with the
SADR0 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up
resistor.
14
FBOUT_NC#
OUT
Complementary half of differential feedback output. This pin should NOT be
connected to anything outside the chip. It exists to provide delay path matching to
get 0 propagation delay.
15
FBOUT_NC
OUT
True half of differential feedback output. This pin should NOT be connected to
anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
16
GND
GND
Ground pin.
17
DIF0
OUT
Differential true clock output
18
DIF0#
OUT
Differential Complementary clock output
19
DIF1
OUT
Differential true clock output
20
DIF1#
OUT
Differential Complementary clock output
21
VDDIO
PWR
Power supply for differential outputs
22
GND
GND
Ground pin.
23
DIF2
OUT
Differential true clock output
24
DIF2#
OUT
Differential Complementary clock output
25
DIF3
OUT
Differential true clock output
26
DIF3#
OUT
Differential Complementary clock output
27
GND
GND
Ground pin.
28
VDD
PWR
Power supply, nominal 3.3V
29
DIF4
OUT
Differential true clock output
30
DIF4#
OUT
Differential Complementary clock output
31
DIF5
OUT
Differential true clock output
32
DIF5#
OUT
Differential Complementary clock output
33
VDDIO
PWR
Power supply for differential outputs
34
GND
GND
Ground pin.
35
DIF6
OUT
Differential true clock output
36
DIF6#
OUT
Differential Complementary clock output


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