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9ZXL1950 Datasheet(Fiches technique) 6 Page - Integrated Device Technology

Numéro de pièce 9ZXL1950
Description  19-output DB1900Z Low-Power Derivative w/85ohm Terminations
Télécharger  18 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

9ZXL1950 Datasheet(HTML) 6 Page - Integrated Device Technology

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19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 6
REVISION E 11/20/15
9ZXL1950 DATASHEET
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Ambient Operating
Temperature
TCOM
Commmercial range
0
35
70
°C
Input High Voltage
VIH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2VDD + 0.3
V
Input Low Voltage
VIL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND - 0.3
0.8
V
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
5
uA
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
Fibyp
VDD = 3.3 V, Bypass mode
33
150
MHz
2
Fipll
VDD = 3.3 V, 100MHz PLL mode
90
100.00
110
MHz
2
Fipll
VDD = 3.3 V, 133.33MHz PLL mode
120
133.33
147
MHz
2
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs, except DIF_IN
1.5
5
pF
1
CINDIF_IN
DIF_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.65
1
ms
2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
31.5
33
kHz
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
25
300
us
1,3
Tfall
tF
Fall time of control inputs
5
ns
1,2
Trise
tR
Rise time of control inputs
5
ns
1,2
SMBus Input Low Voltage
VILSMB
0.8
V
SMBus Input High Voltage
VIHSMB
2.1
VDDSMB
V
SMBus Output Low Voltage
VOLSMB
@ IPULLUP
0.4
V
SMBus Sink Current
IPULLUP
@ VOL
4mA
Nominal Bus Voltage
VDDSMB
3V to 5V +/- 10%
2.7
5.5
V
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA Fall Time
tFSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
SMBus Operating
Frequency
fSMB
SMBus operating frequency
100
kHz
5
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
5The differential input clock must be running for the SMBus to be active
Capacitance
Input Current
Input Frequency


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