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CS5301 Fiches technique(PDF) 6 Page - ON Semiconductor

No de pièce CS5301
Description  Three-Phase Buck Controller with Integrated Gate Drivers and Power Good
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CS5301 Fiches technique(HTML) 6 Page - ON Semiconductor

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ELECTRICAL CHARACTERISTICS (continued) (0
°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8.0 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RROSC = 53.6 k, CCOMP = 0.1 µF, CREF = 0.1 µF, DAC Code 10000, CVCC = 1.0 µF, ILIM ≥ 1.0 V;
unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
Voltage Feedback Error Amplifier
VFB Bias Current, (Note 2)
0.9 V < VFB < 1.8 V
5.5
6.0
6.5
µA
COMP Source Current
COMP = 0.5 V to 2.0 V;
VFB = 1.6 V; DAC = 00000
15
30
60
µA
COMP Sink Current
COMP = 0.5 V to 2.0 V;
VFB = 1.8 V; DAC = 00000
15
30
60
µA
COMP Discharge Threshold Voltage
0.20
0.27
0.34
V
Transconductance
–10
µA < ICOMP < +10 µA
32
mmho
Output Impedance
2.5
M
Open Loop DC Gain
Note 3.
60
90
dB
Unity Gain Bandwidth
0.01
µF COMP Capacitor
400
kHz
PSRR @ 1.0 kHz
70
dB
COMP Max Voltage
VFB = 1.65 V COMP Open;
DAC = 00000
2.4
2.7
V
COMP Min Voltage
VFB = 1.8 V COMP Open;
DAC = 00000
0.1
0.2
V
Hiccup Latch Discharge Current
2
5.0
10
µA
PWM Comparators
Minimum Pulse Width
Measured from CSx to GATE(H),
V(VFB) = V(CSREF) = 0 V,
V(COMP) = 0.5 V, 60 mV step
applied between VCSX and VCREF
350
515
ns
Channel Startup Offset
V(CS1) = V(CS2) = V(CS3) =
V(VFB) = V(CSREF) = 0 V;
Measure V(COMP) when
GATE1(H), 2(H), 3(H) switch high
0.3
0.4
0.5
V
GATE(H) and GATE(L)
High Voltage (AC)
Note 3. Measure VCCLX – GATE(L)
or VCCHX – GATE(H)
0
1.0
V
Low Voltage (AC)
Note 3. Measure GATE(L)
or GATE(H)
0
0.5
V
Rise Time GATE(H)x
1.0 V < GATE < 8.0 V; VCCHX = 10 V
35
80
ns
Rise Time GATE(L)x
1.0 V < GATE < 8.0 V; VCCLX = 10 V
35
80
ns
Fall Time GATE(H)x
8.0 V > GATE > 1.0 V; VCCHX = 10 V
35
80
ns
Fall Time GATE(L)x
8.0 V > GATE > 1.0 V; VCCLX = 10 V
35
80
ns
GATE(H) to GATE(L) Delay
GATE(H) < 2.0 V, GATE(L) > 2.0 V
30
65
110
ns
GATE(L) to GATE(H) Delay
GATE(L) < 2.0 V, GATE(H) > 2.0 V
30
65
110
ns
GATE Pull–down
Force 100
µA into GATE Driver
with VCCHX = VCCLX = 2.0 V
1.2
1.6
V
2. The VFB Bias Current changes with the value of RROSC per Figure 4.
3. Guaranteed by design. Not tested in production.


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