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LM2612 Datasheet(Fiches technique) 14 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numéro de pièce LM2612
Description  400mA Sub-miniature, Programmable, Step-Down DC-DC Converter for Ultra Low-Voltage Circuits
Télécharger  19 Pages
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Fabricant  NSC [National Semiconductor (TI)]
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LM2612 Datasheet(HTML) 14 Page - National Semiconductor (TI)

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PWM Operation (Continued)
PFM Operation
Connecting the SYNC/MODE pin to SGND sets the LM2612
to hysteretic PFM operation. While in PFM (Pulse Frequency
Modulation) mode, the output voltage is regulated by switch-
ing with a discrete energy per cycle and then modulating the
cycle rate, or frequency, to control power to the load. This is
done by using an error comparator to sense the output
voltage and control the PFET switch. The device waits as the
load discharges the output filter capacitor, until the output
voltage drops below the lower threshold of the PFM error-
comparator. Then the error comparator initiates a cycle by
turning on the PFET switch. This allows current to flow from
the input, through the inductor to the output, charging the
output filter capacitor. The PFET switch is turned off when
the output voltage rises above the regulation threshold of the
PFM error comparator. After the PFET switch turns off, the
output voltage rises a little higher as the inductor transfers
stored energy to the output capacitor by pushing current into
the output cacitor. Thus, the output voltage ripple in PFM
mode is proportional to the hysteresis of the error compara-
tor and the inductor current.
In PFM mode, the device only switches as needed to service
the load. This lowers current consumption by reducing power
consumed during the switching action in the circuit due to
transition losses in the internal MOSFETs, gate drive cur-
rents, eddy current losses in the inductor, etc. It also im-
proves light-load voltage regulation. During the second part
of the cycle, the intrinsic body diode of the NFET synchro-
nous rectifier conducts until the inductor current ramps to
zero. The LM2612 does not turn on the synchronous rectifier
while in PFM mode.
Operating Mode Selection
The SYNC/MODE digital input pin is used to select between
PWM or PFM operating modes. Set SYNC/MODE high
(above 1.3V) for 600kHz PWM operation when the system is
active and the load is above 50mA. Set SYNC/MODE low
(below 0.4V) to select PFM mode when the load is less than
50mA for precise regulation and reduced current consump-
tion when the system is in standby.The LM2612 has an
over-voltage protection feature that may activate if the de-
vice is left in PWM mode under low-load conditions (<50mA)
to prevent the output voltage from rising too high. See
ervoltage Protection, for more information.
Select modes with the SYNC/MODE pin using a signal with
a slew rate faster than 5V/100µs. Use a comparator Schmitt
trigger or logic gate to drive the SYNC/MODE pin. Do not
leave the pin floating of allow it to linger between logic levels.
These measures will prevent output voltage errors that could
otherwise occur in response to an indeterminate logic state.
Ensure a minimum load to keep the output voltage in regu-
lation when switching modes frequently. The minimum load
requirement varies depending on the mode change fre-
quency. A typical load of 8µA is required when modes are
changed at 100 ms intervals, 85µA for 10 ms and 800µA for
1 ms.
Frequency Synchronization
The SYNC/MODE input can also be used for frequency
synchronization. To synchronize the LM2612 to an external
clock, supply a digital signal to the SYNC/MODE pin with a
voltage swing exceeding 0.4V to 1.3V. During synchroniza-
tion, the LM2612 initiates cycles on the rising edge of the
clock. When synchronized to an external clock, it operates in
PWM mode. The device can synchronize to a 50%
duty-cycle clock over frequencies from 500kHz to 1MHz.
Use the following waveform and duty-cycle guidelines when
applying an external clock to the SYNC/MODE pin. Each
clock cycle should have high and low periods between 1.3µs
and 200ns and a duty cycle between 30% and 70%. The
total clock period should be 2µs or less. Clock under/
overshoot should be less than 100mV below GND or above
DD. When applying noisy clock signals, especially sharp
edged signals from a long cable during evaluation, terminate
the cable at its characteristic impedance; add an RC filter to
the SYNC pin, if necessary, to soften the slew rate and
PWM Mode Switching Waveform
PFM Mode Switching Waveform
B: SW PIN, 2V/div
B: SW PIN, 2V/div
FIGURE 3. Typical Circuit Waveforms in (a) PWM Mode and (b) PFM Mode

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