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AD8390ACP-R2 Fiches technique(PDF) 10 Page - Analog Devices |
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AD8390ACP-R2 Fiches technique(HTML) 10 Page - Analog Devices |
10 / 16 page AD8390 Rev. C | Page 10 of 16 SETTING THE OUTPUT COMMON-MODE VOLTAGE By design, the AD8390’s VOCM pin is internally biased at a voltage equal to the midsupply point (average value of the voltages on VCC and VEE), eliminating the need for external resistors. The high impedance nature of the VOCM pin, however, allows the designer to force it to a desired level with an external low impedance source. It should be noted that the VOCM pin is not intended for use as an ac signal input. The three configurations for the VOCM pin are floating with a single supply, floating with dual supplies, and forcing the pin with an external source. If not externally forcing the VOCM pin, the designer must decouple it to ground with a 0.1 µF capacitor in close proximity to the AD8390. With dual equal supplies (for example, ±12 V) such that the midpoint of the supplies is nominally 0 V, the user may opt to connect the VOCM pin directly to ground, thus eliminating the need for an external decoupling capacitor. POWER-DOWN FEATURES AND THE IADJ PIN The AD8390 offers significant versatility in setting quiescent bias levels for a particular application from full ON to full OFF. This versatility gives the circuit designer the flexibility to maxi- mize efficiency while maintaining optimal levels of performance. Optimizing driver efficiency while delivering the required signal level is accomplished with the AD8390 through the use of two on-chip power management features: two PWDN pins used to select one of four bias modes, and an IADJ pin used for additional power management including fine bias adjustments. PWDN Pins Two digitally programmable logic pins, PWDN1 and PWDN0, may be used to select four different bias levels (see Table 5). These levels start with full power if the IADJ pin is not connected. The top bias level can also start at approximately half of full bias, if the IADJ pin is connected to VEE or to ground in a single-supply configuration, RADJ = 0. The bias level can be controlled with CMOS logic levels (high = 1) applied to the PWDN1 and PWDN0 pins alone or in combination with the IADJ control pin. The digital ground pin (DGND) is the logic ground reference for the PWDN1 and PWDN0 pins. PWDN = (0,0) is the power-down mode of the amplifier. The AD8390 exhibits a low output impedance for PWDN1,0 = (1,1), (1,0), and (0,1). At PWDN1,0 = (0,0), however, the output impedance is undefined. The lowest power mode (0,0) of the AD8390 alone may not be suitable for systems that rely on a high impedance OFF state, such as multiplexing. IADJ Pin The IADJ feature offers users significant flexibility in setting the bias level of the AD8390 by allowing for fine tuning of the bias setting. Use of the IADJ feature is not required for operation of the AD8390. When IADJ is not connected, the bias current in the various power modes is set to approximately 10 mA, 6.7 mA, and 3.8 mA for power modes PWDN1,0 = (1,1), (1,0), and (0,1), respectively, as seen in Table 5. Setting IADJ = VEE for dual-supply operation (or grounding the IADJ pin for single-supply opera- tion) cuts the bias setting approximately in half for each mode. A resistor (RADJ) between IADJ and ground for single-supply operation, or IADJ and VEE for dual-supply operation, allows fine bias adjustment between the bias levels preset by the PWDN pins. Figure 16 and Figure 19 depict the effect of different RADJ values on setting the bias levels. Table 5. PWDN Code Selection Guide PWDN1 PWDN0 RADJ (Ω) IQ (mA) 1 1 ∞ 10.0 1 0 ∞ 6.7 0 1 ∞ 3.8 0 0 ∞ 0.67 1 1 0 5.2 1 0 0 3.8 0 1 0 2.5 0 0 0 0.57 ADSL and ADSL2+ Applications The AD8390 line driver amplifier is an efficient class AB amplifier that is ideal for driving xDSL signals. The AD8390 may be used for driving ADSL or ADSL2+ modulated signals in either direc- tion: upstream from CPE to the CO or downstream from the CO to CPE. ADSL and ADSL2+ Applications Circuit Increased CO port density has made driver power efficiency an important requirement in ADSL and ADSL2+ systems. The lar- gest impact on efficiency is due to the need for back termina- tion of the driver. In the simplest case, this is accomplished with a pair of resistors, each equal to half the reflected line impedance, in series with the outputs of the differential driver. In this scen- ario, half the transmitted power is consumed by the back term- ination resistors. This results in the need for higher turns ratio transformers, which attenuate the receive signal and tend to be more lossy. They also increase current requirements of the dri- ver, effectively reducing headroom because the output devices can no longer swing as close to the rail. To solve this problem, it is common practice to use a combination of negative and positive feedback to synthesize the output impe- dance, thus decreasing the required ohmic value of the back termination. Overall efficiency is improved because less power is wasted in the back termination and a lower turns ratio trans- former can be used without the need for increased supply rails. The application circuit in Figure 24 depicts such an approach, where the positive feedback, negative feedback, and back termi- nation are provided by R2, R3, and RM, respectively. |
Numéro de pièce similaire - AD8390ACP-R2 |
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Description similaire - AD8390ACP-R2 |
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