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S26KL128S Fiches technique(PDF) 81 Page - Cypress Semiconductor |
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S26KL128S Fiches technique(HTML) 81 Page - Cypress Semiconductor |
81 / 98 page S26KL512S / S26KS512S S26KL256S / S26KS256S S26KL128S / S26KS128S Document Number: 001-99198 Rev. *F Page 81 of 98 11. Timing Specifications The following section describes HyperFlash device dependent aspects of timing specifications. 11.1 AC Test Conditions Figure 28. Test Setup Notes: 1. All AC timings assume an input slew rate of 2V/ns. CK/CK# differential slew rate of at least 4V/ns. 2. Input and output timing is referenced to VCCQ/2 or to the crossing of CK/CK#. Figure 29. Input Waveforms and Measurement Levels Note: 1. Input timings for the differential CK/CK# pair are measured from clock crossings. Table 46. Test Specification Parameter All Speeds Units Output Load Capacitance, CL 20 pF Minimum Input Rise and Fall Slew Rates (Note 1) 2.0 V/ns Input Pulse Levels 0.0-VCCQ V Input timing measurement reference levels VCCQ/2 V Output timing measurement reference levels VCCQ/2 V Device Under Test CL VccQ Vss Input VccQ / 2 Measurement Level VccQ / 2 Output |
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