S25FL116K datasheet(69/90 Pages) CYPRESS

No de pièce	S25FL116K

Description	16 Mbit (2 Mbyte), 32 Mbit (4 Mbyte), 64 Mbit (8 Mbyte) 3.0V SPI Flash Memory

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Fabricant	CYPRESS [Cypress Semiconductor]

Site Internet	http://www.cypress.com

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69 / 90 page

Document Number: 002-00497 Rev. *E

Page 69 of 90

S25FL116K, S25FL132K, S25FL164K

8.2.3

64-kB Block Erase (D8h)

The Block Erase command sets all memory within a specified block (64 kbytes) to the erased state of all 1s (FFh). A Write Enable

command must be executed before the device will accept the Block Erase command (Status Register bit WEL must equal 1). The

command is initiated by driving the CS# pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0)

See Supply and Signal Ground (VSS) on page 10. The Block Erase command sequence is shown in Figure 8.9.

The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase command

will not be executed. After CS# is driven high, the self-timed Block Erase command will commence for a time duration of tBE (see

Section 4.8, AC Electrical Characteristics on page 25). While the Block Erase cycle is in progress, the Read Status Register

command may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and

becomes a 0 when the cycle is finished and the device is ready to accept other commands again. After the Block Erase cycle has

finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase command will not be executed if the

addressed sector is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Section 6.5, Status Registers

on page 50).

Figure 8.9 64-kB Block Erase Command Sequence

8.2.4

Chip Erase (C7h / 60h)

The Chip Erase command sets all memory within the device to the erased state of all 1’s (FFh). A Write Enable command must be

executed before the device will accept the Chip Erase command (Status Register bit WEL must equal 1). The command is initiated

by driving the CS# pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase command sequence is shown in

Figure 8.10.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase command will not be

executed. After CS# is driven high, the self-timed Chip Erase command will commence for a time duration of tCE (Section 4.8, AC

Electrical Characteristics on page 25). While the Chip Erase cycle is in progress, the Read Status Register command may still be

accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and

the device is ready to accept other commands again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the

Status Register is cleared to 0. The Chip Erase command will not be executed if any page is protected by the Block Protect (CMP,

SEC, TB, BP2, BP1, and BP0) bits (see Section 6.5, Status Registers on page 50).

Figure 8.10 Chip Erase Command Sequence

CS#

SCK

SI

SO

Phase

76

543

210

23

1

0

Instruction

Address

CS#

SCK

SI

SO

Phase

7

6

5

4

3

2

1

0

Instruction

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