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CY8C4128FNI-BL473 Fiches technique(PDF) 16 Page - Cypress Semiconductor |
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CY8C4128FNI-BL473 Fiches technique(HTML) 16 Page - Cypress Semiconductor |
16 / 47 page PRELIMINARY PSoC® 4: PSoC 4XX8_BLE Family Datasheet Document Number: 001-94624 Rev. *K Page 16 of 47 The possible pin connections are shown for all analog and digital peripherals (except the radio, LCD, and CSD blocks, which were shown in Table 1). A typical system application connection diagram is shown in Figure 7. Figure 7. System Application Connection Diagram Power The PSoC 4XX8_BLE device can be supplied from batteries with a voltage range of 1.9 V to 5.5 V by directly connecting to the digital supply (VDDD), analog supply (VDDA), and radio supply (VDDR) pins. Internal LDOs in the device regulate the supply voltage to the required levels for different blocks. The device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation. Analog circuits run directly from the analog supply (VDDA) input. The device uses separate regulators for Deep Sleep and Hibernate (lowered power supply and retention) modes to minimize the power consumption. The radio stops working below 1.9 V, but the device continues to function down to 1.71 V without RF. Bypass capacitors must be used from VDDx (x = A, D, or R) to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (for example, 0.1 µF). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. VDDR VDDD VDDR VDDA VDDA VDDR VDDD C6 C1 1.0 uF U1 PSoC 4XXX_BLE 56-QFN VDDD 1 XTAL32O/P6.0 2 XTAL32I/P6.1 3 XRES 4 P4.0 5 P5.0 7 P5.1 8 VSS 9 VDDR 10 GANT1 11 ANT 12 GANT2 13 VDDR 14 P4.1 6 P1.1 29 P1.2 30 P1.3 31 P1.4 32 P1.5 33 P1.6 34 P1.7 35 P2.0 37 P2.1 38 P2.2 39 P2.3 40 P2.4 41 P2.5 42 VDDA 36 Y2 32.768KHz 1 2 C4 18 pF C3 36 pF C2 1.0 uF Y1 24MHz 2 4 L1 ANTENNA C5 1.3 47 pF 24 pF Power Supply Bypass Capacitors VDDD The internal bandgap may be bypassed with a 1-µF to 10-µF. VDDA 0.1-µF ceramic at each pin plus bulk capacitor 1-µF to 10-µF. VDDR 0.1-µF ceramic at each pin plus bulk capacitor 1-µF to 10-µF. VCCD 1.3-µF ceramic capacitor at the VCCD pin. VREF (optional) The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor. |
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