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CY8C4128FNI-BL473 Fiches technique(PDF) 8 Page - Cypress Semiconductor |
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CY8C4128FNI-BL473 Fiches technique(HTML) 8 Page - Cypress Semiconductor |
8 / 47 page PRELIMINARY PSoC® 4: PSoC 4XX8_BLE Family Datasheet Document Number: 001-94624 Rev. *K Page 8 of 47 Programmable Digital Universal Digital Blocks (UDBs) and Port Interfaces The PSoC 4XX8_BLE has four UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control. Figure 5. UDB Array UDBs can be clocked from a clock-divider block, from a port interface (required for peripherals such as SPI), and from the DSI network directly or after synchronization. A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside the UDB array. This allows a faster operation because the inputs and outputs can be registered at the port interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of the I/Os from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating the delay for the port input to be routed over DSI and used to register other inputs (see Figure 6). Figure 6. Port Interface UDBs can generate interrupts (one UDB at a time) to the interrupt controller. UDBs retain the ability to connect to any pin on the chip through the DSI. P rogram m a ble D ig ital S u bsyste m UDB IF UD B UD B UD B UD B DS I DS I DS I DS I BU S IF CLK IF Port IF P ort IF Port IF CP U S ub -sys tem Sy stem Interconne ct C lo cks 4 to 8 8 to 32 R o uting C hannels IR Q IF Clock Selector Block from UDB 9 Digital GlobalClocks 3 DSI Signals , 1 I/O Signal 4 Reset Selector Block from UDB 2 2 Input Registers Output Registers To DSI 8 From DSI 8 8 8 Enables 8 From DSI 4 4 7 6 . . . 0 7 6 . . . 0 3 2 1 0 High Speed I/O Matrix To Clock Tree [0] [0] [1] [1] [1] [1] |
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