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MB95F818KPMC-G-UNE2 Fiches technique(PDF) 100 Page - Cypress Semiconductor

No de pièce MB95F818KPMC-G-UNE2
Description  New 8FX 8-bit Microcontrollers
Download  121 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB95F818KPMC-G-UNE2 Fiches technique(HTML) 100 Page - Cypress Semiconductor

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MB95810K Series
Document Number: 002-04694 Rev. *A
Page 100 of 121
(VCC = 5.0 V
10%, VSS = 0.0 V, TA = 40 °C to 85 °C)
Parameter Symbol
Pin
name
Condition
Value*2
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW
SCL
R = 1.7 k
,
C = 50 pF*1
(2
 nm/2)tMCLK  20
ns Master mode
SCL clock
“H” width
tHIGH
SCL
(nm/2)tMCLK
 20
(nm/2)tMCLK
 20
ns Master mode
START
condition
hold time
tHD;STA
SCL,
SDA0
(-1
 nm/2)tMCLK  20 (-1  nm)tMCLK  20
ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value is
applied.
STOP
condition
setup time
tSU;STO
SCL,
SDA
(1
 nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode
START
condition
setup time
tSU;STA
SCL,
SDA
(1
 nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode
Bus free time
between
STOP
condition
and START
condition
tBUF
SCL,
SDA
(2 nm
 4) tMCLK  20
ns
Data hold
time
tHD;DAT
SCL,
SDA
3 tMCLK
 20
ns Master mode
Data setup
time
tSU;DAT
SCL,
SDA
(-2
 nm/2) tMCLK  20 (-1  nm/2) tMCLK  20 ns
Master mode
It is assumed that
“L” of SCL is not
extended. The
minimum value is
applied to the first
bit of continuous
data. Otherwise,
the maximum
value is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL
(nm/2) tMCLK
 20 (1  nm/2) tMCLK  20 ns
The minimum
value is applied
to the interrupt at
the ninth SCL
.
The maximum
value is applied
to the interrupt at
the eighth SCL
.
SCL clock
“L” width
tLOW
SCL
4 tMCLK
 20
ns At reception
SCL clock
“H” width
tHIGH
SCL
4 tMCLK
 20
ns At reception


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