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BCM20730 Datasheet(Fiches technique) 51 Page - Cypress Semiconductor

Numéro de pièce BCM20730
Description  Single-Chip Bluetooth Transceiver for Wireless Input Devices
Télécharger  62 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

BCM20730 Datasheet(HTML) 51 Page - Cypress Semiconductor

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Timing and AC Characteristics
BROADCOM
September 9, 2013 • 20730-DS108-R
Page 50
®
BCM20730 Data Sheet
BROADCOM CONFIDENTIAL
Table 20: SPI1 Timing Values—SCLK = 6 MHz and VDDM = 1.62Va
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
Reference Characteristics
Symbol
Min
Typicalb
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 6 MHz.
Max
Unit
1
Output setup time, from MOSI data
valid to sample edge of SCLK
Tds_mo
41
ns
2
Output hold time, from sample
edge of SCLK to MOSI data update
Tdh_mo
120
ns
3
Input setup time, from MISO
data valid to sample edge of SCLK
Tds_mi
TBD
ns
4
Input hold time, from sample
edge of SCLK to MISO data update
Tdh_mi
TBD
ns
5c
c. CS timing is firmware controlled.
Time from CS assert to first SCLK
edge
Tsu_cs
½ SCLK period – 1
ns
6c
Time from first SCLK edge to CS
deassert
Thd_cs
½ SCLK period
ns
Table 21: SPI2 Timing Values—SCLK = 12 MHz and VDDM = 3.2Va
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
Reference Characteristics
Symbol
Min
Typicalb
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.
Max
Unit
1
Output setup time, from MOSI
data valid to sample edge of SCLK
Tds_mo
26
ns
2
Output hold time, from sample
edge of SCLK to MOSI data update
Tdh_mo
56
ns
3
Input setup time, from MISO
data valid to sample edge of SCLK
Tds_mi
TBD
ns
4
Input hold time, from sample
edge of SCLK to MISO data update
Tdh_mi
TBD
ns
5c
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
Time from CS assert to first SCLK
edge
Tsu_cs
½ SCLK period – 1
ns
6c
Time from first SCLK edge to CS
deassert
Thd_cs
½ SCLK period
ns


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