CS8412 datasheet(11/38 Pages) CIRRUS

No de pièce	CS8412

Description	DIGITAL AUDIO INTER FACE RECEIVER

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Fabricant	CIRRUS [Cirrus Logic]

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CS8411 CS8412

DS61F1

11

PARITY, CODE and LOCK bits are latches which

are set when their corresponding conditions occur,

and are reset when SR2 is read. The ERF pin is as-

serted each time the error occurs assuming the in-

terrupt enable bit in IER2 is set for that particular

error. When the ERF pin is asserted, the ERF bit in

SR1 is set. If the ERF bit was not set prior to the

ERF pin assertion, an interrupt will be generated

(assuming bit 3 in IER1 is set). Although the ERF

pin is asserted for each occurrence of an enabled er-

ror condition, the ERF bit will only cause an inter-

rupt once if SR1 is not read.

V is the validity status bit which is set any time the

received validity bit is high. PARITY is set when a

parity error is detected. CODE is set when a bi-

phase coding error is detected. LOCK is asserted

when the receiver PLL is not locked and occurs

when there is no input on RXP/RXN, or if the re-

ceived frequency is out of the receiver lock range

(25 kHz to 55 kHz). Lock is achieved after receiv-

ing three frame preambles followed by one block

preamble, and is lost after four consecutive frame

preambles are not received.

The upper three bits in SR2, FREQ2-FREQ0, can

report the receiver frequency when the receiver is

locked. These bits are only valid when FCEN in

control register 1 is set, and a 6.144 MHz clock is

applied to the FCK pin. When FCEN is set, the

A4/FCK pin is used as FCK and A4 is internally set

to zero; therefore, only the lower half of the buffer

can be accessed. Table 1 lists the frequency ranges

reported. The FREQ bits are updated three times

per block and the clock on the FCK pin must be val-

id for two thirds of a block for the FREQ bits to be

accurate. The vast majority of audio systems must

meet the 400 ppm tolerance listed in the table. The

4% tolerance is provided for unique situations

where the approximate frequency needs to be

known, even though that frequency is outside the

normal audio specifications.

Table 1. Incoming Sample Frequency Bits

IEnable register 2 has corresponding interrupt en-

able bits for the first five bits in SR2. A "1" enables

the condition in SR2 to cause ERF to go high, while

a "0" masks that condition. Bit 5 is unused and bits6

and 7, the two most significant bits, are factory test

bits and must be set to zero when writing to this

register. The CS8411 sets these bits to zero on pow-

er-up.

Control Registers

The CS8411 contains two control registers. Control

register1 (CR1), at address 2, selects system level

features, while control register 2 (CR2), at address

3, configures the audio serial port.

In control register 1, when RST is low, all outputs

are reset except MCK (FSYNC and SCLK are high

impedance). After the user sets RST high, the

CS8411 comes fully out of reset when the block

boundary is found. It is recommended to reset the

CS8411 after power-up and any time the user per-

forms a system-wide reset. The serial port, in mas-

ter mode, will begin to operate as soon as RST goes

Figure 7. Status/IEnable Register 2

SR2:

FREQ2:

The 3 FREQ bits indicate incoming sample frequency.

FREQ1:

(must have 6.144 MHz clock on FCK pin and FCEN

FREQ0:

must be “1”)

LOCK:

Out-of-Lock error

CODE:

Coding violation

PARITY:

Parity error

V:

Validity bit high

IER2: TEST1,0:

(0 on power-up) Must stay at “0”.

INT. ENABLES: Enables the corresponding bit in SR2.

A “1” enables the interrupt. A “0” masks the interrupt.

X:01

765

4

3

2

1

0

SR2.

FREQ2 FREQ1 FREQ0 Reserved LOCK CODE PARITY

V

IER2. TEST1

TEST0

INT. ENABLE BITS

FOR ABOVE

FREQ2 FREQ1 FREQ0

Sample Frequency

0

Out of Range

00

1

48 kHz ± 4%

0

1

0

44.1 kHz ± 4%

0

1

32 kHz ± 4%

1

0

48 kHz ± 400 ppm

1

0

1

44.1 kHz ± 400 ppm

1

0

44.056 kHz ± 400 ppm

1

32 kHz ± 400 ppm

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