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ZL40518 Fiches technique(PDF) 3 Page - Zarlink Semiconductor Inc

No de pièce ZL40518
Description  3 Channel Laser Diode Driver
Download  16 Pages
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Fabricant  ZARLINK [Zarlink Semiconductor Inc]
Site Internet  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

ZL40518 Fiches technique(HTML) 3 Page - Zarlink Semiconductor Inc

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ZL40518
Data Sheet
3
Zarlink Semiconductor Inc.
signal will be clipped on the negative cycle of the signal. This will increase the harmonic content of the output signal
and reduce the pk to pk amplitude output.
Thermal Considerations
Package thermal resistance is 40
° C/W under the EIA/JESD51-3 compliant PCB test board condition. Users should
ensure that the junction temperature does not exceed 150
°C. Thermal resistance from junction to case and to
ambient is very much dependent on how the IC is mounted onto the board, on the PCB layout and on any heat
extraction arrangements. Power consumption and system ambient operating temperature limits should be noted
and careful thermal gradient calculations undertaken to ensure that the junction temperature never exceeds 150
°C.
Electrical and Optical Pulse Response
Figure 3 - Pulse Response Model
Figure 3 illustrates a simplified model of the typical ZL40518 and the application. The ZL40518 consist of an ideal
switched current source and an equivalent model of the ZL40518 output stage. The Electrical Model for the Laser
Diode is a Voltage source Vd (V_on) in series with the On Resistance Rd all in parallel with the Junction
Capacitance Cd. This simplified model approximately represents the Laser Diode Electrical load when operated
beyond the Laser Threshold. To a first approximation, the Optical output is proportional to the current flow in the
Resistor Rd.
The Laser Diode and the ZL40518 are connected together by interconnect tracks with the return current passing
through the supply decoupling bypass capacitor between ground and output Vcc. The ZL40518 will typically switch
the programmed output current in 400 ps and can be approximated to an ideal switch with a propagation delay of
Iout_on (1.2 nS). The electrical pulse response parameters, Trise, Tfall, Overshoot and Undershoot are determined
by the combined electrical network as illustrated in Figure 3.
For example, the Rise Time and Fall time for large current steps can be slew rate limited by the combined
interconnect and fixed interconnect inductance. The Fixed Inductance represents that associated with packaging
and minimum interconnect distance . The Interconnect Inductance is that associated with the additional tracking
between Laser Diode and the ZL40518 to accommodate application physical limitations.
For example, if a pulse of 260 mA amplitude (40 mA to 300 mA) is to be switched in a time of 1 ns with the Vd =
1.6 V, then the maximum volt drop across the interconnect inductance is approximately 3.5 V (maximum Vpin for
300 mA output) - 1.6 V (Vdiode) = 1.9 V. Consequently, L*di/dt < 1.9 V. Hence , L < 1.9/ (0.26A/1ns)
= 7.3 nH.
En
Iout
500
17p
15
2p
ZL40518 Model
Vd
Rd
Cd
Lint
C_out
Lfix = 3nH
Lint=5nH , BW = 460MHz, Rd=7, Q=j20/(15+7) =0.9
Lint=5nH, BW = 460MHz, Rd=3, Q=j20/(15+3) = 1.11
Lint=7nH, BW = 411MHz, Rd=7, Q=j18/(15+7) = 0.8
Lint=7nH, BW = 411MHz, Rd=3, Q=j18/(15+3) = 1.0
Lint
Lfix = 3nH
C_bypass
K
K
Vcc_A
OutA


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