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TS80C31X2-VLBR Fiches technique(PDF) 8 Page - ATMEL Corporation |
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TS80C31X2-VLBR Fiches technique(HTML) 8 Page - ATMEL Corporation |
8 / 42 page 8 Rev. C - 15 January, 2001 TS80C31X2 Table 3. CKCON Register CKCON - Clock Control Register (8Fh) Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com) 7 6 5 4 3 2 1 0 - - - - - - - X2 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 X2 CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL). |
Numéro de pièce similaire - TS80C31X2-VLBR |
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Description similaire - TS80C31X2-VLBR |
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