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LM1881N-X Fiches technique(PDF) 6 Page - National Semiconductor (TI) |
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LM1881N-X Fiches technique(HTML) 6 Page - National Semiconductor (TI) |
6 / 12 page Application Notes (Continued) flip-flop is toggled by the default comparator, starting the vertical sync pulse at pin 3 of the LM1881. If the default vertical sync period ends before the end of the input vertical sync period, then the falling edge of the vertical sync (posi- tive pulse at the “D” flip-flop) will clock the high output from the comparator with V 1 as a reference input. This will retrig- ger the oscillator, generating a second vertical sync output pulse. The “Vertical Default Sync Delay Time vs R SET” graph shows the relationship between the R SET value and the delay time from the start of the vertical sync period before the default vertical sync pulse is generated. Using the NTSC example again the smallest resistor for R SET is 500 k Ω. The vertical default time delay is about 50 µs, much longer than the 30 µs serration pulse spacing. A common question is how can one calculate the required R SET with a video timing standard that has no serration pulses during the vertical blanking. If the default vertical sync is to be used this is a very easy task. Use the “Vertical Default Sync Delay Time vs R SET” graph to select the nec- essary R SET to give the desired delay time for the vertical sync output signal. If a second pulse is undesirable, then check the “Vertical Pulse Width vs R SET” graph to make sure the vertical output pulse will extend beyond the end of the input vertical sync period. In most systems the end of the vertical sync period may be very accurate. In this case the preferred design may be to start the vertical sync pulse at the end of the vertical sync period, similar to starting the vertical sync pulse after the first serration pulse. A VGA standard is to be used as an example to show how this is done. In this standard a horizontal line is 32 µs long. The vertical sync period is two horizontal lines long, or 64 µs. The vertical default sync delay time must be longer than the vertical sync period of 64 µs. In this case R SET must be larger than 680 k Ω.R SET must still be small enough for the output of the integrator to reach V 1 before the end of the vertical period of the input pulse. The first graph can be used to confirm that R SET is small enough for the integrator. Instead of using the vertical serration pulse separation, use the actual pulse width of the vertical sync period, or 64 µs in this example. This graph is linear, meaning that a value as large as 2.7 M Ω can be used for R SET (twice the value as the maximum at 30 µs). Due to leakage currents it is advisable to keep the value of R SET under 2.0 M Ω. In this example a value of 1.0 M Ω is selected, well above the minimum of 680 kΩ. With this value for R SET the pulse width of the vertical sync output pulse of the LM1881 is about 340 µs. 00915003 FIGURE 1. (a) Composite Video; (b) Composite Sync; (c) Vertical Output Pulse; (d) Odd/Even Field Index; (e) Burst Gate/Back Porch Clamp www.national.com 6 |
Numéro de pièce similaire - LM1881N-X |
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Description similaire - LM1881N-X |
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