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MC100LVEL11DR2G Fiches technique(PDF) 2 Page - ON Semiconductor

No de pièce MC100LVEL11DR2G
Description  ECL 1:2 Differential Fanout Buffer
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100LVEL11DR2G Fiches technique(HTML) 2 Page - ON Semiconductor

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MC100LVEL11
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Table 1. PIN DESCRIPTION
Pin
Function
Q0, Q0; Q1, Q1
ECL Data Outputs
D, D
ECL Data Inputs
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad must be connected to a suffi-
cient thermal conduit. Electrically connect to the most negative
supply (GND) or leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
W
Internal Input Pullup Resistor
75 k
W
ESD Protection
Human Body Model
Machine Model
Charge Device Model
> 4 KV
> 400 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
63
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI  VCC
VI  VEE
6 to 0
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +95
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lpfm
500 lpfm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lpfm
500 lpfm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
Pb−Free
<2 to 3 sec @ 260
°C
265
°C
qJC
Thermal Resistance (Junction−to−Case)
(Note 2)
DFN8
35 to 40
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)


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