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TL331-EP Fiches technique(PDF) 3 Page - Texas Instruments

No de pièce TL331-EP
Description  SINGLE DIFFERENTIAL COMPARATOR
Download  11 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TL331-EP Fiches technique(HTML) 3 Page - Texas Instruments

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TL331-EP
www.ti.com
SLVSBU6 – JUNE 2013
THERMAL INFORMATION
TL331-EP
THERMAL METRIC(1)
DBV
UNITS
5 PINS
θJA
Junction-to-ambient thermal resistance(2)
299
θJCtop
Junction-to-case (top) thermal resistance(3)
65.4
θJB
Junction-to-board thermal resistance(4)
97.1
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.8
ψJB
Junction-to-board characterization parameter(6)
95.5
θJCbot
Junction-to-case (bottom) thermal resistance(7)
N/A
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VCC = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
TA
MIN
TYP
MAX
UNIT
25°C
2
5
VCC = 5 V to 30 V, VO = 1.4 V,
VIO
Input offset voltage
mV
VIC = VIC(min)
–55°C to 125°C
9
25°C
5
50
IIO
Input offset current
VO = 1.4 V
nA
–55°C to 125°C
250
25°C
–25
–250
IIB
Input bias current
VO = 1.4 V
nA
–55°C to 125°C
–400
0 to
25°C
VCC – 1.5
Common-mode input voltage
VICR
V
range(2)
0 to
–55°C to 125°C
VCC – 2
Large-signal differential-voltage
VCC = 15 V, VO = 1.4 V to 11.4 V,
AVD
25°C
50
200
V/mV
amplification
RL ≥ 15 kΩ to VCC
VOH = 5 V, VID = 1 V
25°C
0.1
50
nA
IOH
High-level output current
VOH = 30 V, VID = 1 V
–55°C to 125°C
1
μA
25°C
150
400
VOL
Low-level output voltage
IOL = 4 mA, VID = –1 V
mV
–55°C to 125°C
700
IOL
Low-level output current
VOL = 1.5 V, VID = –1 V
25°C
6
mA
ICC
Supply current
RL = ∞, VCC = 5 V
25°C
0.4
0.7
mA
(1)
All characteristics are measured with zero common-mode input voltage, unless otherwise specified.
(2)
The voltage at either input or common-mode should not be allowed to go negative by more than 0.3 V. The upper end of the common-
mode voltage range is VCC+ – 1.5 V, but either or both inputs can go to 30 V without damage.
Copyright © 2013, Texas Instruments Incorporated
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