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SA8027 Fiches technique(PDF) 12 Page - NXP Semiconductors

No de pièce SA8027
Description  2.5 GHz low voltage, low power RF fractional-N/IF integer frequency synthesizer
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SA8027 Fiches technique(HTML) 12 Page - NXP Semiconductors

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Philips Semiconductors
Product data
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
2001 Aug 21
12
2.0
SERIAL PROGRAMMING BUS
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 11
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
data is latched into the selected working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A, in that order. A typical programming sequence is
illustrated in Figure 12. Table 2 shows the format and the contents of
each word. The D word is used for testing purposes and should be
initially set to 0 for normal operation. When sending the B-word, data
bits FC7–0 for the fractional compensation DAC are not loaded
immediately. Instead they are stored in temporary registers. Only
when the A-word is loaded, these temporary registers are loaded
together with the main divider ratio.
2.1
Serial bus timing characteristics (see Figure 11)
VDD = VDDCP =+3.0 V; Tamb = +25 °C unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
tr
Input rise time
10
40
ns
tf
Input fall time
10
40
ns
Tcy
Clock period
100
ns
Enable programming; STROBE
tSTART
Delay to rising clock edge
40
ns
tW
Minimum inactive pulse width
1/fCOMP
ns
tSU;E
Enable set-up time to next clock edge
20
ns
Register serial input data; DATA
tSU;DAT
Input data to clock set-up time
20
ns
tHD;DAT
Input data to clock hold time
20
ns
Application information
SR01417
CLK
DATA
STROBE
LSB
ADDRESS
tSU;DAT
tHD;DAT
tf
tw
tr
tSU;E
tSTART
Tcy
MSB
≥ 0
Figure 11.
Serial Bus Timing Diagram


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