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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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P87LPC760 Fiches technique(PDF) 30 Page - NXP Semiconductors |
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P87LPC760 Fiches technique(HTML) 30 Page - NXP Semiconductors |
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30 / 56 page  Philips Semiconductors Preliminary data P87LPC760 Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP 2002 Mar 07 27 Timer/Counters The P87LPC760 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate as timers or can be configured to be an event counter (see Figure 22). An option to automatically toggle the T0 pin upon timer overflow has been added. In the “Timer” function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 6 CPU clock periods, the count rate is 1/6 of the CPU clock frequency. Refer to the section Enhanced CPU for a description of the CPU clock. In the “Counter” function of Timer 0, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0. In this function, the external input is sampled once during every machine cycle. When the samples of the pin state show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes 2 machine cycles (12 CPU clocks) to recognize a 1-to-0 transition, the maximum count rate is 1/6 of the CPU clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. The “Timer” or “Counter” function of Timer 0 is selected by control bit C/T in the Special Function Register TMOD. In addition to the “Timer” or “Counter” selection, Timer 0 and Timer 1 have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text. BIT SYMBOL FUNCTION TMOD.7, 6 – Reserved. Must be written with zeros only. TMOD.5, 4 M1, M0 Mode Select for Timer 1 (see table below). TMOD.3 GATE Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0 pin is high and the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set. TMOD.2 C/T Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from internal system clock.) Set for Counter operation (input from T0 input pin). TMOD.1, 0 M1, M0 Mode Select for Timer 0 (see table below). M1, M0 Timer Mode 0 0 8048 Timer “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter “THn” and “TLn” are cascaded; there is no prescaler. 1 0 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows. 1 1 Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text). Timer 1 in this mode is stopped. M0 SU01542 M1 C/T GATE M0 M1 – – 0 1 2 3 4 5 6 7 TMOD Reset Value: 00h Not Bit Addressable Address: 89h T1 T0 Figure 22. Timer/Counter Mode Control Register (TMOD) |
Numéro de pièce similaire - P87LPC760 |
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Description similaire - P87LPC760 |
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