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ILC6383CIRADJX Fiches technique(PDF) 7 Page - Fairchild Semiconductor |
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ILC6383CIRADJX Fiches technique(HTML) 7 Page - Fairchild Semiconductor |
7 / 15 page PRODUCT SPECIFICATION ILC6383 REV. 1.2.6 6/13/02 7 The Dual PWM/PFM mode architecture was designed spe- cifically for applications such as wireless communications, which need the spectral predictability of a PWM-type DC- DC converter, yet also need the highest efficiencies possible, especially in Standby mode. Other Considerations The other limitation of PWM techniques is that, while the fundamental switching frequency is easier to filter out since it's constant, the higher order harmonics of PWM will be present and may have to be filtered out, as well. Any filtering requirements, though, will vary by application and by actual system design and layout, so generalizations in this area are difficult, at best. However, PWM control for boost DC-DC conversion is widely used, especially in audio-noise sensitive applications or applications requiring strict filtering of the high frequency components. Low Battery Detector The ILC6383's low battery detector is a based on a CMOS comparator. The negative input of the comparator is tied to an internal 1.25V (nominal) reference, VREF. The positive input is the LBI/SD pin. It uses a simple potential divider arrangement with two resistors to set the LBI threshold as shown in Figure 6. The input bias current of the LBI pin is only 200nA. This means that the resistor values R1 and R2 can be set quite high. The formula for setting the LBI thresh- old is: VLBI = VREF x (1+R5/R6) Since the LBI input current is negligible (<200nA), this equation is derived by applying voltage divider formula across R6. A typical value for R6 is 100k Ω. R5 = 100k Ω x [(VLBI/VREF) -1], where VREF = 1.25V (nom.) The LBI detector has a built in delay of 120ms. In order to get a valid low-battery-output (LBO) signal, the input volt- age must be lower than the low-battery-input (LBI) threshold for a duration greater than the low battery hold time (thold(LBI)) of 120msec. This feature eliminates false trigger- ing due to voltage transients at the battery terminal caused by high frequency switching currents. Figure 6. Low Battery Detector The output of the low battery detector is an open drain capable of sinking 2mA. A 10k Ω pull-up resistor is recom- mended on this output. For VLBI < 1.25V The low battery detector can also be configured for voltages <1.25V by bootstrapping the LBI input from VOUT. The circuitry for this is shown in Figure 7. Figure 7. VLBI < 1.25V The following equation is used when VIN is lower than 1.25V: R1 = R2 x [(VREF - VIN) / (VOUT - VREF)], where VREF = 1.25V (nom.) This equation can also be derived using voltage divider formula across R2. A typical value for R2 is 100k Ω. R6 R5 LBI/SD 3 2 VIN ILC6383 Shutdown DELAY 100ms 1.25V Internal Reference GND 7 LBO 3.3V RPU 6 + - VOUT 8 R2 3 LBI/SD VIN R1 ILC6383 + - 1.25V Internal Reference GND 7 |
Numéro de pièce similaire - ILC6383CIRADJX |
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Description similaire - ILC6383CIRADJX |
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