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ST92185B2BJ1 Fiches technique(PDF) 6 Page - STMicroelectronics

No de pièce ST92185B2BJ1
Description  16K/24K/32K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY
Download  178 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST92185B2BJ1 Fiches technique(HTML) 6 Page - STMicroelectronics

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ST92185B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92185B microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The ST92185B MCU supports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which in-
cludes the control and status registers of the on-
chip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine
remains frozen
(the
clock is
also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete sys-
tem for TV set and VCR applications:
– Voltage Synthesis
– Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 char-
acter set. The character resolution is 10x10 dot.
Four character sizes are supported. Serial at-
tributes allow the user to select foreground and
background colors, character size and fringe back-
ground. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
Note: The OSD cell is common to all ST92x195
family devices. However, its capabilities are limit-
ed by a TDSRAM memory size of 2Kbytes on the
ST92185 family. Certain display modes using
more than 2Kbytes of memory are not available.


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