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ADM1023 Fiches technique(PDF) 12 Page - ON Semiconductor

No de pièce ADM1023
Description  ACPI‐Compliant, High Accuracy Microprocessor System Temperature Monitor
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADM1023 Fiches technique(HTML) 12 Page - ON Semiconductor

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12
Table 12. DEVICE ADDRESSES (Note 1)
ADD0
ADD1
Device Address
0
0
0011 000
0
NC
0011 001
0
1
0011 010
NC
0
0101 001
NC
NC
0101 010
NC
1
0101 011
1
0
1001 100
1
NC
1001 101
1
1
1001 110
1. ADD0 and ADD1 are sampled at powerup only.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high-to-low transition
on the serial data line, SDATA, while the serial
clock line, SCLK, remains high. This indicates
that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the start condition and shift in the next 8 bits.
These bits consist of a 7-bit address (MSB first)
plus an R/W bit, which determines the direction of
the data transfer, that is, whether data is written to,
or read from, the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge bit. All
other devices on the bus remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is 0, the master writes
to the slave device. If the R/W bit is 1, the master
reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, 8 bits of data followed by an
Acknowledge bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, because a low-to-high
transition when the clock is high may be
interpreted as a stop signal. The number of data
bytes that can be transmitted over the serial bus in
a single read or write operation is limited only by
what the master and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
clock pulse to assert a stop condition. In read
mode, the master device overrides the
Acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
then takes the data line low during the low period
before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
Figure 15. Writing a Register Address to the Address Pointer Register,
then Writing Data to the Selected Register
R/W
0
SCLK
SDATA
10
1
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1023
START BY
MASTER
19
1
ACK. BY
ADM1023
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1023
STOP BY
MASTER
1
9
SCLK (CONTINUED)
SDATA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
Figure 16. Writing to the Address Pointer Register Only
0
SCLK
SDATA
10
1
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1023
START BY
MASTER
19
1
ACK. BY
ADM1023
9
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
R/W


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