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TSC2100IDA Fiches technique(PDF) 9 Page - Texas Instruments |
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TSC2100IDA Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 77 page TSC2100 SLAS378− NOVEMBER 2003 www.ti.com 9 AUDIO INTERFACE TIMING DIAGRAMS LRCK/ADWS BCLK DOUT DIN td (WS) td (DO−WS) td (DO−BCLK) ts (DI) th (DI) Figure 1. I2S/LJF/RJF Timing in Master Mode TYPICAL TIMING REQUIREMENTS (FIGURE 1) All specifications at 25°C, DVDD = 1.8 V (1) PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER MIN MAX MIN MAX UNITS td (WS) ADWS/LRCK delay 25 15 ns td (DO−WS) ADWS to DOUT delay (for LJF mode) 25 15 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns tr Rise time 10 6 ns tf Fall time 10 6 ns (1) These parameters are based on characterization and are not tested in production. LRCK/ADWS BCLK DOUT DIN td (WS) td (DO−BCLK) ts (DI) th (DI) td (WS) Figure 2. DSP Timing in Master Mode TYPICAL TIMING REQUIREMENTS (FIGURE 2) All specifications at 25°C, DVDD = 1.8 V(1) PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER MIN MAX MIN MAX UNITS td (WS) ADWS/LRCK delay 25 15 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns tr Rise time 10 6 ns tf Fall time 10 6 ns (1) These parameters are based on characterization and are not tested in production. |
Numéro de pièce similaire - TSC2100IDA |
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Description similaire - TSC2100IDA |
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