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AS4C16M16D1A Fiches technique(PDF) 59 Page - Alliance Semiconductor Corporation |
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AS4C16M16D1A Fiches technique(HTML) 59 Page - Alliance Semiconductor Corporation |
59 / 64 page Figure 39. Write without Auto Precharge CK CK A0-A8 NOP COMMAND tIS tIH NOP NOP NOP VALID tIS tIH tCH tCL tCK RA CKE A10 BA0,BA1 DQS NOP WRITE RA tIH tIS DQ tDSH PRE NOP NOP ACT Col n tIS tIH RA ALL BANKS ONE BANKS Bank X tIS tIH DIS AP *Bank X BA tWPRES Case 1: tDQSS=min DI n tIH tDQSS tDSH tDQSH tDQSL tWPST tWPRE DM DQS DQ tDSS tWPRES Case 2: tDQSS=max DI n tDQSS tDSS DM tWR tRP tDQSH tWPST tDQSL tWPRE Don’t Care DI n = Data In from column n PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH Burst Length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks A9,A11,A12 16Mx16 DDR1-AS4C16M16D1A Confidential - 59/64 - Rev.1.1 July 2015 |
Numéro de pièce similaire - AS4C16M16D1A |
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Description similaire - AS4C16M16D1A |
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