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TPS92602A-Q1 Fiches technique(PDF) 4 Page - Texas Instruments |
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TPS92602A-Q1 Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 47 page TPS92601-Q1, TPS92602-Q1, TPS92601A-Q1, TPS92602A-Q1 SLUSBP5D – MARCH 2014 – REVISED JANUARY 2015 www.ti.com Pin Functions (continued) PIN TPS92601-Q1 TPS92602-Q1 I/O DESCRIPTION NAME TPS92601A-Q1 TPS92602A-Q1 20 PINS 28 PINS PWMO1 20 28 O PWM PMOS-FET driver output (channel 1) PWMO2 — 14 O PWM PMOS-FET driver output (channel 2) RT 4 4 I Oscillator pin and pin for external sync. frequency VCC 13 21 O Gate-drive supply voltage (external decoupling capacitor) VIN 8 8 I Supply voltage VOUT1 19 27 I Connect to boost output voltage (channel 1) VOUT2 — 15 I Connect to boost output voltage (channel 2) Thermal pad — Solder to achieve appropriate power dissipation. Connect to PGND. 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) (3) over operating free-air temperature (unless otherwise noted) MIN MAX UNIT Supply voltage VIN, PWMINx(4) –0.3 40 V Output voltage VOUTx, ISPx, ISNx, PWMOx (4) –0.3 80 V Differential voltage (VOUTx – PWMOx)(4) –0.3 8.8 V Grounds PGNDx(4) –0.3 0.3 V GDRVx, ISNSx (4) –0.3 8.8 V OVFBx(4) –0.3 80 V Other pins VCC –0.3 8.8 V ICTRLx, COMPx, RT, DIAGx (4) –0.3 3.6 V VCC current Gate-driver supply 220 mA Junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) The algebraic convention, whereby the most-negative value is a minimum and the most-positive value is a maximum. (3) All voltages are with respect to ground (GND pin), unless otherwise specified. (4) ()or the TPS9602-Q1 device, x = 1 or 2. For the TPS9601-Q1 device, x is blank. 7.2 ESD Ratings VALUE UNIT Human-body model (HBM), per AEC Q100-002(1) ±2000 Other pins ±500 V(ESD) Electrostatic discharge V Charged-device model (CDM), per Corner pins (1, 14, 15, 28 for AEC Q100-011 TPS92602x-Q1; 1, 10, 11, 20 for ±750 RPS92601x-Q1) (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 4 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPS92601-Q1 TPS92602-Q1 TPS92601A-Q1 TPS92602A-Q1 |
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