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PN7360AUHN Fiches technique(PDF) 34 Page - NXP Semiconductors

No de pièce PN7360AUHN
Description  NFC Cortex-M0 microcontroller
Download  86 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

PN7360AUHN Fiches technique(HTML) 34 Page - NXP Semiconductors

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PN746X_736X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.1 — 5 April 2016
369231
34 of 86
NXP Semiconductors
PN746X_736X
NFC Cortex-M0 microcontroller
The down-mixed differential RX input signals are passed to the BBA and a band-pass
filter. For considering all the protocols (type A/B, FeliCa), the high-pass cut-off frequency
of BBA is configured between 45 kHz and 250 kHz. The configuration is done in four
different steps. The low-pass cut-off frequency is greater than 2 MHz.
The output of band-pass filter is further amplified with a gain factor which is configurable
between 30 dB and 60 dB. The baseband amplifier (BBA)/ADC I-channel and Q-channel
can be enabled separately. It is required for ADC-based card mode functionality as only
the I-channel is used in this case.
VMID: A resistive divider between AVDD and GND generates VMID. The resistive divider
is connected to the VMID pin. An external blocking capacitor of typical value 100 nF is
connected.
Automatic Gain Control (AGC):
The contactless interface AGC is used to control the 
amplitude of 13.56 MHz sine‐wave input signal received. The signal is received at the 
antenna connected between the pins RXP and RXN. A comparator is used to compare the 
peak value of the input signal with a reference voltage.
A voltage divider circuit is used to generate the reference voltage. An external resistor 
(typically 3.3 k) is connected to the RX input, which forms a voltage divider with an 
on‐chip variable resistor. The voltage divider circuit so formed has a 10‐bit resolution.
Note: The comparator monitors the RXP signal only.
By varying the on-chip resistor, the amplitude of the input signal can be modified. The
value of on-chip resistor is increased or decreased, depending on the output of the
sampled comparator. The on-chip resistor value is adjusted until the peak of the input
signal matches the reference voltage. Thus, the AGC circuit automatically controls the
amplitude of the RX input.
The internal amplitude controlling resistor in the AGC has a default value of 10 K
. It
means that, when the resistor control bits in AGC_VALUE_REG <9:0> are all 0, the
resistance is 10 K
. As the control bits are increased, resistors are switched in parallel to
the 10 K
 resistor. It lowers the resultant resistance value to 5 k (AGC_VALUE_REG
<9:0>, all bits set to 1).
Mode detector: The mode detector is a functional block of the PN7462 which senses for
an RF field generated by another device. The mode detector facilitates to distinguish
between type A and Felica target mode. The host responds depending on the recognized
protocol generated by an initiator peer device.
Fig 22. Receiver block diagram


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