TPS71025

LOW-DROPOUT VOLTAGE REGULATOR

SLVS162A – MAY 1997 – REVISED MAY 1998

11

POST OFFICE BOX 655303

THERMAL INFORMATION

In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch

surface-mount packages. Implementation of many of today’s high-performance devices in these packages

requires special attention to power dissipation. Many system-dependent issues such as thermal coupling,

airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components

affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are illustrated in this discussion:

Figure 16 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout

system is illustrated in Figure 17. The family of curves illustrates the effect of increasing the size of the

copper-heat-sink surface area. The PWB is a standard FR4 board (L

× W × H = 3.2 inch × 3.2 inch × 0.062 inch);

the board traces and heat sink area are 1-oz (per square foot) copper.

Copper Heat Sink

1 oz Copper

Figure 16. Thermally Enhanced PWB Layout (Not to Scale) for the 20-Pin TSSOP

Figure 18 shows the thermal resistance for the same system with the addition of a thermally conductive

compound between the body of the TSSOP package and the PWB copper routed directly beneath the device.

The thermal conductivity for the compound used in this analysis is 0.815 W/m

× °C.