TPS737

SBVS067Q – JANUARY 2006 – REVISED MAY 2015

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6.4 Thermal Information

DRB [VSON]

DCQ

DRV

UNIT

[SOT-223]

8 PINS

6 PINS

6 PINS

49.5

53.1

67.2

58.9

35.2

87.6

25.1

7.8

36.8

°C/W

1.7

2.9

1.8

25.2

7.7

37.2

8.6

N/A

7.7

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as

specified in the JESD51 series. The following assumptions are used in the simulations:

(a)

i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.

pad, 0.8-mm pitch array is used which is off the JEDEC standard.

(b) The top copper layer has a detailed copper trace pattern. The bottom copper layer is assumed to have a 20% thermal conductivity of

copper, representing a 20% copper coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area.

To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction

Temperature sections of this data sheet.

(3)

Power dissipation may limit operating range.

(4)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(5)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(6)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(7)

The junction-to-top characterization parameter,

from the simulation data to obtain

(8)

The junction-to-board characterization parameter,

from the simulation data to obtain

(9)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6

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