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STK57FU394AG-E Fiches technique(PDF) 7 Page - ON Semiconductor |
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STK57FU394AG-E Fiches technique(HTML) 7 Page - ON Semiconductor |
7 / 13 page STK531U394A-E www.onsemi.com 7 Input / Output Timing Chart Fig. 7 Notes *1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be added externally. *2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. When VDD rises the operation will resume immediately. *3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gate voltage rises. *4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18 to 80ms after the over current condition is removed. ON OFF HIN1,2,3 LIN1,2,3 N terminal (BUS line) current Upper U, V, W Lower U ,V, W VB1,2,3 *1 *1 OFF ON *2 *3 VBS under voltage protection reset signal VDD under voltage protection reset signal -------------------------------------------------------ISD operation current level------------------------------------------------------- Utmatically reset after protection (18ms to 80ms) *4 VDD VBS under voltage protection reset signal FAULT terminal voltage (at pulled-up) |
Numéro de pièce similaire - STK57FU394AG-E |
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Description similaire - STK57FU394AG-E |
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