ADV7181B datasheet(10/96 Pages) AD

No de pièce	ADV7181B

Description	Multiformat SDTV Video Decoder

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ADV7181B

Rev. 0 | Page 10 of 96

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

HS

2

DGND

3

DVDDIO

4

P11

5

P10

6

P9

7

P8

8

SFL

9

DGND 10

DVDDIO 11

NC 12

NC 13

P7 14

P6 15

P5 16

AIN5

48

AIN4

47

AIN3

46

AGND

45

CAPC2

44

AGND

43

CML

42

REFOUT

41

AVDD

40

CAPY2

39

CAPY1

38

AGND

37

AIN2

36

AIN1

35

DGND

34

NC

33

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

ADV7181B

TOP VIEW

(Not to Scale)

NC = NO CONNECT

PIN 1

INDICATOR

INTRQ

Figure 4. 64-Lead LFCSP/LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Function

3, 10, 24, 34, 57

DGND

G

Digital Ground.

32, 37, 43, 45

AGND

G

Analog Ground.

4, 11

DVDDIO

P

Digital I/O Supply Voltage (3.3 V).

23, 58

DVDD

P

Digital Core Supply Voltage (1.8 V).

40

AVDD

P

Analog Supply Voltage (3.3 V).

31

PVDD

P

PLL Supply Voltage (1.8 V).

35, 36, 46–49

AIN1–AIN6

I

Analog Video Input Channels.

12, 13, 27, 28, 33,

50, 55, 56

NC

No Connect Pins.

26, 25, 19, 18, 17,

16, 15, 14, 8, 7, 6, 5,

62, 61, 60, 59

P0–P15

O

Video Pixel Output Port.

2

HS

O

Horizontal Synchronization Output Signal.

64

VS

O

Vertical Synchronization Output Signal.

63

FIELD

O

Field Synchronization Output Signal.

1

INTRQ

O

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input

video. See the interrupt register map in Table 82.

53

SDA

I/O

I2C Port Serial Data Input/Output Pin.

54

SCLK

I

I2C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).

52

ALSB

I

This pin selects the I2C address for the ADV7181B. ALSB set to a Logic 0 sets the address for

a write as 0x40; for ALSB set to a logic high, the address selected is 0x42.

51

RESET

I

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7181B circuitry.

20

LLC

O

This is a line-locked output clock for the pixel data output by the ADV7181B. Nominally

27 MHz, but varies up or down according to video line length.

22

XTAL

I

This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,

27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

Numéro de pièce similaire - ADV7181B

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Analog Devices	ADV7181B	2Mb / 100P	Multiformat SDTV Video Decoder Rev. B

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