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AD5160BRJ10-R2 Fiches technique(PDF) 5 Page - Analog Devices

No de pièce AD5160BRJ10-R2
Description  256-Position SPI Compatible Digital Potentiometer
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5160BRJ10-R2 Fiches technique(HTML) 5 Page - Analog Devices

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AD5160
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 3.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
Clock Frequency
fCLK
25
MHz
Input Clock Pulsewidth
tCH, tCL
Clock level high or low
20
ns
Data Setup Time
tDS
5
ns
Data Hold Time
tDH
5
ns
CS Setup Time
tCSS
15
ns
CS High Pulsewidth
tCSW
40
ns
CLK Fall to CS Fall Hold Time
tCSH0
0
ns
CLK Fall to CS Rise Hold Time
tCSH1
0
ns
CS Rise to Clock Rise Setup
tCS1
10
ns
NOTES
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 4.
Parameter
Value
VDD to GND
–0.3 V to +7 V
VA, VB, VW to GND
VDD
IMAX1
±20 mA
Digital Inputs and Output Voltage to GND
0 V to +7 V
Operating Temperature Range
–40°C to +125°C
Maximum Junction Temperature (TJMAX)
150°C
Storage Temperature
–65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C
Thermal Resistance2 θJA: MSOP-10
230°C/W
NOTES
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 16


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