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Si5342A-D-GM Fiches technique(PDF) 11 Page - Silicon Laboratories

No de pièce Si5342A-D-GM
Description  10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier
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Fabricant  SILABS [Silicon Laboratories]
Site Internet  http://www.silabs.com
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3.7.7 Synchronizing to Gapped Input Clocks
The DSPLL supports locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of
gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely
increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic
clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For
example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock.
This is shown in the following figure. For more information on gapped clocks, see “AN561: Introduction to Gapped Clocks and PLLs”.
DSPLL
100 ns
100 ns
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
100 MHz clock
1 missing period every 10
90 MHz non-gapped clock
10 ns
11.11111... ns
Gapped Input Clock
Periodic Output Clock
Period Removed
Figure 3.5. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every eight. Lock-
ing to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the
hitless switching specification in Table 5.8 Performance Characteristics on page 31 when the switch occurs during a gap in either
input clock.
3.8 Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the fig-
ure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is
also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL loses synchronization.
DSPLL
LPF
PD
÷M
IN0
IN0b
Precision
Fast
OOF
LOS
÷P0
IN1
IN1b
Precision
Fast
OOF
LOS
÷P1
IN3/FB_IN
IN3/FB_INb
Precision
Fast
OOF
LOS
÷P3
IN2
IN2b
Precision
Fast
OOF
LOS
÷P2
LOL
XB
XA
OSC
LOS
Si5345/44/42
Figure 3.6. Si5345/44/42 Fault Monitors
Si5345/44/42 Rev D Data Sheet
Functional Description
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 10


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