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TPS62002DGS Fiches technique(PDF) 3 Page - Texas Instruments

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No de pièce TPS62002DGS
Description  TPS6200x High-Efficiency Step-Down Low Power DC-DC Converter
Download  31 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS62002DGS Fiches technique(HTML) 3 Page - Texas Instruments

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1
2
3
4
5
10
9
8
7
6
VIN
FC
GND
PG
FB
PGND
L
EN
SYNC
ILIM
TPS62000, TPS62001, TPS62002, TPS62003
TPS62004, TPS62005, TPS62006, TPS62007, TPS62008
www.ti.com
SLVS294F – SEPTEMBER 2000 – REVISED AUGUST 2015
5 Device Comparison Table
PACKAGE(1)
MARKING
VOLTAGE OPTIONS
VSSOP
DGS
Adjustable
TPS62000DGS
AIH
0.9 V
TPS62001DGS
AII
1 V
TPS62002DGS
AIJ
1.2 V
TPS62003DGS
AIK
1.5 V
TPS62004DGS
AIL
1.8 V
TPS62005DGS
AIM
1.9 V
TPS62008DGS
AJI
2.5 V
TPS62006DGS
AIN
3.3 V
TPS62007DGS
AIO
(1)
For shipment quantities and additional package information see Mechanical, Packaging, and Orderable Information
6 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the
EN
8
I
supply current to less than 1
μA.
Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is
FB
5
I
connected to FB. The internal voltage divider is disabled for the adjustable version.
Supply bypass pin. A 0.1-
μF coupling capacitor should be connected as close as possible to this pin for
FC
2
good high frequency input voltage supply filtering.
GND
3
Ground
Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this
ILIM
6
I
pin to VIN to set the current limit to typically 1200 mA.
L
9
I/O
Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.
Power good comparator output. This is an open-drain output. A pull-up resistor should be connected
PG
4
O
between PG and VOUT. The output goes active high when the output voltage is greater than 92% of the
nominal value.
PGND
10
Power ground. Connect all power grounds to PGND.
Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an
external clock signal with CMOS level:
SYNC
7
I
SYNC = High: Low-noise mode enabled, fixed frequency PWM operation is forced
SYNC = Low (GND): Power save mode enabled, PFM/PWM mode enabled
VIN
1
I
Supply voltage input
Copyright © 2000–2015, Texas Instruments Incorporated
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Product Folder Links: TPS62000 TPS62001 TPS62002 TPS62003 TPS62004 TPS62005 TPS62006 TPS62007
TPS62008


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