TPS62404QDRCRQ1 datasheet(8/42 Pages) TI1

No de pièce	TPS62404QDRCRQ1

Description	2.25-MHz 400-mA and 600-mA Dual Step-Down Converter

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Fabricant	TI1 [Texas Instruments]

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TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1

SLVSA67E – FEBRUARY 2010 – REVISED JUNE 2015

www.ti.com

Electrical Characteristics (continued)

VIN = 3.6 V, VOUT1 = VOUT2 = 1.8 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to

125°C, typical values are at TJ = 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage positioning active,

MODE/DATA = GND,

VOUTx(PFM)

–1.5%

1%

2.5%

device operating in PFM mode,

VIN = 2.5 V to 5 V

(6) (7)

DC output voltage accuracy adjustable and

MODE/DATA = GND;

fixed output voltage(5)

device operating in PWM mode,

–1%

0%

1%

VIN = 2.5 V to 6 V

(7)

VOUTx(PWM)

VIN = 2.5 V to 6 V, MODE/DATA = VIN ,

Fixed PWM operation,

–1%

0%

1%

0 mA < IOUT1 < 400 mA ; 0 mA < IOUT2 < 600 mA

(8)

DC output voltage load regulation

PWM operation mode

0.5

%/A

(5)

Output voltage specification does not include tolerance of external voltage-programming resistors.

(6)

Configuration L1 or L2 typ. 2.2

μH, COUTx typ 20 μF. See parameter measurement information, the output voltage ripple in PFM mode

depends on the effective capacitance of the output capacitor; larger output capacitors lead to tighter output voltage tolerance.

(7)

In power-save mode, the device typically enters PWM operation at IPSM = VIN / 32 Ω.

(8)

For VOUTx > 2 V, VIN min = VOUTx + 0.5 V

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

INTERFACE TIMING

tStart

Start time

2

μs

tH_LB

High-time low bit, logic 0 detection

Signal level on MODE/DATA pin is > 1.2 V

2

200

μs

tL_LB

Low-time low bit, logic 0 detection

Signal level on MODE/DATA pin < 0.4 V

2 x tH_LB

400

μs

tL_HB

Low-time high bit, logic 1 detection

Signal level on MODE/DATA pin < 0.4 V

2

200

μs

tH_HB

High-time high bit, logic 1 detection

Signal level on MODE/DATA pin is > 1.2 V

2 x tL_HB

400

μs

tEOS

End of stream

2

μs

Duration of acknowledge condition

tACKN

(MODE/DATE line pulled low by the

VIN 2.5 V to 6 V

400

520

μs

device)

tvalACK

Acknowledge valid time

2

μs

ttimeout

Time-out for entering power-save mode

MODE/DATA pin changes from high to low

520

μs

7.7 Switching Characteristics

VIN = 3.6 V, VOUT1 = VOUT2 = 1.8 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to

125°C, typical values are at TJ = 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OSCILLATOR

2.5 V

≤ VIN ≤ 6 V; TPS62400-Q1

1.7

2.3

2.7

adjustable version(1)

3.0 V

≤ VIN ≤ 6 V; TPS62400-Q1,

fSW

Oscillator frequency

2

2.3

2.7

MHz

TPS62402-Q1, TPS62404-Q1(1)

3.6 V

≤ VIN ≤ 5.1 V; TPS62405-Q1

2.06

2.2

2.49

fixed output voltage version(1)

OUTPUT

tStart up

Start-up time

Activation time to start switching(2)

170

μs

Time to ramp from 5% to 95% of

tRamp

VOUTx ramp-up time

750

μs

VOUTx

(1)

For VOUTx > 2 V, VIN min = VOUTx + 0.5 V

(2)

This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) with the other converter already

enabled (for example, EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = 0) to active mode (EN1

and/or EN2 = 1), a typical value of typ 80

μs for ramp up of internal circuits must be added. After tStart, the converter starts switching and

ramps VOUTx.

8

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Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1

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