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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS62400-Q1 Fiches technique(PDF) 11 Page - Texas Instruments |
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TPS62400-Q1 Fiches technique(HTML) 11 Page - Texas Instruments |
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11 / 42 page  TPS62400-Q1, TPS62402-Q1, TPS62404-Q1, TPS62405-Q1 www.ti.com SLVSA67E – FEBRUARY 2010 – REVISED JUNE 2015 9 Detailed Description 9.1 Overview The TPS62400-Q1 device includes two synchronous step-down converters. The converters operate with typically 2.25-MHz fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. With the power- safe mode enabled, the converters automatically enter power-save mode at light load currents and operate in PFM (pulse frequency modulation). During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with input- voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch turns on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET turns off and the N-channel MOSFET turns on. If the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit. The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and converter 2 decreases the input rms current. 9.1.1 Converter 1 In the adjustable output-voltage version, TPS62400-Q1 device, one can set the converter 1 default output voltage via an external resistor network on the DEF_1 pin, which operates as an analog input. In this case, one can set the output voltage in the range of 0.6 V to VIN V. The FB1 pin must directly connect to the converter 1 output voltage VOUT1. It feeds back the output voltage directly to the regulation loop. One can also change the output voltage of converter 1 with the EasyScale serial Interface. This makes the device very flexible for output-voltage adjustment. In this case, the device uses an internal resistor network. In the fixed default output voltage version, TPS62402-Q1 for example, the DEF_1 pin configuration is as a digital input. Converter 1 defaults to 1.2 V or 1.8 V, depending on the level of the DEF_1 pin. If DEF_1 is low, the default is 1.2 V; if high, the default is 1.8 V. With the EasyScale interface, one can change the output voltage for each DEF_1 pin condition (high or low). 9.1.2 Converter 2 In the adjustable output-voltage version, TPS62400-Q1 device, an external resistor divider connected to ADJ2 pin sets the converter 2 output voltage. The converter uses an external feed-forward capacitor of 33 pF. In fixed output-voltage version TPS62402-Q1 for example, the fixed default output voltage is fixed to 3.3 V. In this case, the ADJ2 pin must connect directly to the converter 2 output voltage,VOUT2. It is also possible to change the output voltage of converter 2 via the EasyScale interface. In this case, the ADJ2 pin must connect directly to converter 2 output voltage VOUT2, with no connection of external resistors permitted. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS62400-Q1 TPS62402-Q1 TPS62404-Q1 TPS62405-Q1 |
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