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TPS62150A-Q1 Fiches technique(PDF) 10 Page - Texas Instruments

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No de pièce TPS62150A-Q1
Description  3-V to 17-V, 1-A Step-Down Converter in 3-mm3-mm QFN Package
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS62150A-Q1 Fiches technique(HTML) 10 Page - Texas Instruments

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TPS62150, TPS62150A, TPS62151, TPS62152, TPS62153
SLVSAL5D – NOVEMBER 2011 – REVISED SEPTEMBER 2016
www.ti.com
Product Folder Links: TPS62150 TPS62150A TPS62151 TPS62152 TPS62153
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Feature Description (continued)
Using a very small capacitor (or leaving the SS/TR pin disconnected) provides fastest start-up behavior. There is
no theoretical limit for the longest startup time. The TPS6215x can start into a pre-biased output. During
monotonic pre-biased start-up, both the power MOSFETs are not allowed to turn on until the internal ramp of the
device sets an output voltage above the pre-bias voltage. If the device is set to shutdown (EN = GND),
undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low
level. Returning from those states causes a new start-up sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in
both directions, up and down (see Application and Implementation).
8.3.3 Power Good (PG)
The TPS6215x has a built-in power-good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. One use of the PG signal can be for start-up sequencing of multiple rails. The PG pin is
an open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic-low level. With TPS62150 it it is high impedance when the device is turned off due to
EN, UVLO or thermal shutdown. TPS62150A features PG=Low in this case and can be used to actively
discharge VOUT (see Figure 45). VIN must remain present for the PG pin to stay Low. See SLVA644 for
application details. If not used, the PG pin should be connected to GND but may be left floating.
space
Table 1. Power Good Pin Logic Table (TPS62150)
Device State
PG Logic Status
High Impedance
Low
Enable (EN=High)
VFB ≥ VTH_PG
VFB ≤ VTH_PG
Shutdown (EN=Low)
UVLO
0.7 V < VIN < VUVLO
Thermal Shutdown
TJ > TSD
Power Supply Removal
VIN < 0.7 V
space
Table 2. Power Good Pin Logic Table (TPS62150A)
Device State
PG Logic Status
High Impedance
Low
Enable (EN=High)
VFB ≥ VTH_PG
VFB ≤ VTH_PG
Shutdown (EN=Low)
UVLO
0.7 V < VIN < VUVLO
Thermal Shutdown
TJ > TSD
Power Supply Removal
VIN < 0.7 V
(1)
Maximum allowed voltage is 7 V. Therefore, the recommended connection for DEF is to VOUT, not VIN.
space
8.3.4 Pin-Selectable Output Voltage (DEF)
Setting the DEF pin to High increases the output voltage of the TPS62150x devices by 5% above the nominal
voltage (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage
allows adapting the power supply voltage to the variations of the application hardware. More detailed information
on voltage margining using the TPS62150x device is in SLVA489. The pin has an internally connected pulldown
resistor of about 400 kΩ to ensure a proper logic level if the pin is high-impedance or floating after an initially Low
setting. Setting the pin High disconnects the resistor.


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