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TPS54972PWPG4 Fiches technique(PDF) 5 Page - Texas Instruments

No de pièce TPS54972PWPG4
Description  9-A OUTPUT, 3-V TO 4-V INPUT TRACKING/TERMINATION SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FETs
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS54972PWPG4 Fiches technique(HTML) 5 Page - Texas Instruments

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AGND
VSENSE
COMP
STATUS
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
RT
ENA
REFIN
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
THERMAL
PAD
TPS54972
www.ti.com
SLVS437B – AUGUST 2002 – REVISED AUGUST 2010
TPS54972 Externally Composed Pin-Out
28 Pin HTSSOP PowerPAD
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor, and
SYNC pin. Connect PowerPAD connection to AGND.
BOOT
5
Bootstrap output. 0.022-mF to 0.1-mF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
ENA
27
Enable input. Logic high enables oscillator, PWM control, and MOSFET driver circuits. Logic low disables operation and
places device in a low quiescent current state.
PGND
15-
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
19
the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection
to AGND is recommended.
PH
6-14
Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
REFIN
26
External reference input. High impedance input to slow-start and error amplifier circuits.
STATUS
4
Open drain output. Asserted low when VIN < UVLO, VBIAS and internal reference are not settled or the internal
shutdown signal is active. Otherwise STATUS is high.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-mF to 1.0-mF ceramic capacitor.
VIN
20-
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
24
package with a high-quality, low-ESR 10-mF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
Copyright © 2002–2010, Texas Instruments Incorporated
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