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TPS54362BQPWPRQ1 Fiches technique(PDF) 8 Page - Texas Instruments |
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TPS54362BQPWPRQ1 Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 40 page TPS54362-Q1 SLVS845G – MARCH 2009 – REVISED AUGUST 2014 www.ti.com Electrical Characteristics (continued) V(VIN) = 7 V to 48 V, V(EN) = V(VIN), TJ = –40°C to 150°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST(1) SYNCHRONIZATION (SYNC)(2) VIL(SYNC) Low input threshold 0.7 V PT VIH(SYNC) High input threshold 1.7 V PT Ilkg Leakage SYNC = 5 V 65 95 μA PT Duty(min) Minimum duty cycle 30% CT Duty(miax) Maximum duty cycle 70% CT Rslew Rslew = 50 k Ω 20 I(Rslew) Output current μA CT Rslew = 10 k Ω 100 OVERVOLTAGE SUPERVISORS (OV_TH) Threshold for OV_TH pin during V(OV_TH) Internal switch is OFF. 0.768 0.832 V OV PT Internal pulldown current on OV_TH = 1 V, V(VReg) = 5 V 70 mA OV_TH pin THERMAL SHUTDOWN Thermal shutdown junction T(SD) 175 °C CT temperature T(HYS) Temperature hysteresis 30 °C CT (2) The SYNC input clock can have a maximum frequency of 2× the programmed clock frequency up to a maximum value of 1.1 MHz. 6.6 Timing Requirements V(VIN) = 7 V to 48 V, V(EN) = V(VIN), TJ = –40°C to 150°C (unless otherwise noted) MIN NOM MAX UNIT TEST(1) SYNCHRONIZATION (SYNC)(2) External clock = 1 MHz, V(VIN) = 12 V, t(trans-ItoE) Internal clock to external clock 2.5 μs Info V(VReg) = 5 V V(VIN) = 12 V, V(VReg) = 5 V, f(SYNC) Input clock 180 2200 kHz CT f(sw) < f(ext) < 2 × f(sw) RESET OUTPUT (RST) td(POR) POR delay timer C2 = 4.7 nF 3.6 7 ms PT td(RSTdly) Filter time 10 20 35 μs PT (1) PT = Production tested; CT = Characterization tested only, not production tested; Info = User information only, not production tested (2) The SYNC input clock can have a maximum frequency of 2× the programmed clock frequency up to a maximum value of 1.1 MHz. 6.7 Switching Characteristics V(VIN) = 7 V to 48 V, V(EN) = V(VIN), TJ = –40°C to 150°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST(1) SYNCHRONIZATION (SYNC)(2) t(trans-EtoI) External clock to internal clock Remove external clock, V(VIN) = 12 V, 32 μs Info V(VReg) = 5 V (1) PT = Production tested; CT = Characterization tested only, not production tested; Info = User information only, not production tested (2) The SYNC input clock can have a maximum frequency of 2× the programmed clock frequency up to a maximum value of 1.1 MHz. 8 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: TPS54362-Q1 |
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