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TPS54326PWPR Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS54326PWPR Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 30 page SW1 VBST SS VFB GND 14 7 5 6 2 3 4 1 VREG5 13 12 11 9 8 10 SW2 16 15 SW3 EXPOSED THERMAL PAD TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 RGT PACKAGE (TOP VIEW) PIN FUNCTIONS PIN DESCRIPTION NAME PWP 14 RGT 16 VO 1 16 Connect to output of converter. This pin is used for On-Time Adjustment. VFB 2 1 Converter feedback input. Connect with feedback resistor divider. VREG5 3 2 5.5 V power supply output. A capacitor (typical 1 μF) should be connected to GND. SS 4 3 Soft-start control. A external capacitor should be connected to GND. GND 5 4 Signal ground pin PG 6 5 Open drain power good output EN 7 6 Enable control input PGND1, Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND 8, 9 7, 8 PGND2 and GND strongly together near the IC. Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current SW1, SW2 10, 11 9, 10, 11 comparators. Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to VBST 12 12 respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin. VIN 13 13, 14 Power input and connected to high side NFET drain VCC 14 15 Supply input for 5 V internal linear regulator for the control circuitry Exposed Thermal Back Back Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be Pad or side side connected to PGND. PowerPAD ™ Copyright © 2009–2012, Texas Instruments Incorporated 5 Product Folder Link(s) :TPS54326 |
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